Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34881	1			T7	6		T9	6		T12	2
auto[SpiFlashAddrCfg]	7432	1			T7	4		T9	2		T12	2
auto[SpiFlashAddr3b]	9026	1			T7	4		T19	2		T54	4
auto[SpiFlashAddr4b]	7371	1			T7	2		T11	2		T12	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32165

1

T9

8

T11

2

T12

6

auto[1]

26545

1

T7

16

T54

6

T68

4

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31174

1

T7

4

T12

4

T18

2

auto[1]

27536

1

T7

12

T9

8

T11

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39530	1			T7	6		T9	6		T12	2
values[1]	1100	1			T66	2		T55	5		T94	1
values[2]	1402	1			T38	2		T58	1		T61	2
values[3]	1437	1			T7	2		T19	2		T38	4
values[4]	1382	1			T49	2		T59	2		T55	9
values[5]	1416	1			T7	4		T142	4		T60	2
values[6]	1475	1			T9	2		T142	6		T49	2
values[7]	1338	1			T55	2		T56	3		T45	4
values[8]	9630	1			T7	4		T11	2		T12	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28377

1

T7

16

T9

8

T12

6

auto[1]

30333

1

T11

2

T50

1

T57

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55512

1

T7

16

T9

8

T11

2

write

3198

1

T60

2

T61

2

T55

11

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18517

1

T7

8

T9

2

T11

2

valids[0x1]

40193

1

T7

8

T9

6

T12

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1496	1			T12	2		T18	2		T38	2
internal_process_ops[0x5a]	1568	1			T7	2		T19	2		T38	2
internal_process_ops[0x05]	21494	1			T7	2		T38	2		T59	2
internal_process_ops[0x35]	1500	1			T7	4		T9	6		T38	2
internal_process_ops[0x15]	1604	1			T17	2		T19	6		T38	4
internal_process_ops[0x03]	1038	1			T54	2		T50	1		T59	4
internal_process_ops[0x0b]	1033	1			T54	2		T57	2		T64	4
internal_process_ops[0x3b]	987	1			T11	2		T58	2		T64	6
internal_process_ops[0x6b]	1062	1			T9	2		T49	2		T55	2
internal_process_ops[0xbb]	987	1			T7	2		T59	2		T57	1
internal_process_ops[0xeb]	1017	1			T38	2		T61	2		T55	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57076

1

T7

16

T9

8

T11

2

auto[1]

1634

1

T55

7

T94

2

T56

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56400

1

T7

16

T9

8

T11

2

auto[1]

2310

1

T55

11

T56

11

T45

5

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8792

1

T9

6

T12

2

T17

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6341

1

T7

6

T64

2

T93

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1945

1

T9

2

T12

2

T142

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1762

1

T7

4

T68

2

T64

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2403

1

T19

2

T38

6

T142

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2075

1

T7

4

T54

4

T68

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1931

1

T12

2

T38

4

T49

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1677

1

T7

2

T54

2

T64

16

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

88

1

T62

6

T63

1

T211

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

86

1

T73

1

T212

1

T213

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

93

1

T73

3

T51

1

T211

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

85

1

T73

2

T211

2

T78

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

99

1

T63

2

T72

1

T73

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

95

1

T77

1

T211

3

T214

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

69

1

T73

1

T211

3

T215

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

93

1

T70

4

T51

4

T76

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

129

1

T63

3

T71

4

T216

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

88

1

T72

1

T217

3

T215

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

78

1

T72

2

T73

1

T77

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

82

1

T69

2

T70

2

T72

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

95

1

T60

2

T61

2

T63

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

98

1

T72

1

T217

1

T77

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

77

1

T63

3

T215

1

T214

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

96

1

T63

1

T73

2

T79

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10629

1

T55

88

T94

12

T56

29

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8335

1

T55

178

T94

3

T56

226

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1515

1

T57

2

T58

1

T55

16

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1408

1

T55

19

T94

2

T56

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1806

1

T57

1

T58

2

T55

24

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1946

1

T55

21

T94

9

T56

9

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1502

1

T11

2

T50

1

T55

23

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1445

1

T55

13

T94

2

T56

18

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

110

1

T55

1

T112

2

T129

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

94

1

T55

1

T112

1

T129

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

98

1

T56

1

T45

4

T111

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

130

1

T55

1

T56

2

T111

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

97

1

T55

1

T56

4

T112

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

138

1

T55

3

T45

1

T113

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

98

1

T218

2

T219

1

T125

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

113

1

T113

2

T129

1

T40

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

94

1

T220

2

T218

2

T221

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

118

1

T94

2

T45

1

T129

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

101

1

T55

2

T45

2

T40

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

106

1

T55

1

T45

1

T112

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

122

1

T45

2

T112

3

T129

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

91

1

T56

2

T45

1

T112

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

116

1

T129

2

T219

1

T144

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

121

1

T55

1

T220

1

T221

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3406	1			T20	6		T38	2		T68	2
auto[0]	values[0]	valids[0x1]	14452	1			T7	6		T9	6		T12	2
auto[0]	values[1]	valids[0x1]	553	1			T66	2		T95	2		T63	3
auto[0]	values[2]	valids[0x0]	534	1			T38	2		T61	2		T63	4
auto[0]	values[2]	valids[0x1]	281	1			T92	4		T63	2		T73	3
auto[0]	values[3]	valids[0x0]	517	1			T38	2		T63	1		T222	2
auto[0]	values[3]	valids[0x1]	258	1			T7	2		T19	2		T38	2
auto[0]	values[4]	valids[0x0]	475	1			T49	2		T65	2		T63	3
auto[0]	values[4]	valids[0x1]	265	1			T59	2		T63	1		T88	4
auto[0]	values[5]	valids[0x0]	495	1			T7	4		T142	4		T60	2
auto[0]	values[5]	valids[0x1]	298	1			T65	2		T63	1		T88	2
auto[0]	values[6]	valids[0x0]	523	1			T9	2		T49	2		T59	2
auto[0]	values[6]	valids[0x1]	283	1			T142	6		T68	2		T87	2
auto[0]	values[7]	valids[0x0]	459	1			T63	2		T88	2		T118	4
auto[0]	values[7]	valids[0x1]	307	1			T71	2		T223	2		T73	2
auto[0]	values[8]	valids[0x0]	3291	1			T7	4		T12	4		T54	2
auto[0]	values[8]	valids[0x1]	1980	1			T38	2		T60	2		T66	4
auto[1]	values[0]	valids[0x0]	4050	1			T55	40		T94	6		T56	22
auto[1]	values[0]	valids[0x1]	17622	1			T50	1		T57	2		T55	242
auto[1]	values[1]	valids[0x1]	547	1			T55	5		T94	1		T56	5
auto[1]	values[2]	valids[0x0]	350	1			T55	4		T94	1		T56	2
auto[1]	values[2]	valids[0x1]	237	1			T58	1		T55	1		T56	1
auto[1]	values[3]	valids[0x0]	390	1			T55	2		T94	4		T56	7
auto[1]	values[3]	valids[0x1]	272	1			T55	5		T94	1		T56	1
auto[1]	values[4]	valids[0x0]	401	1			T55	5		T94	4		T56	4
auto[1]	values[4]	valids[0x1]	241	1			T55	4		T94	1		T56	1
auto[1]	values[5]	valids[0x0]	365	1			T55	9		T94	4		T56	1
auto[1]	values[5]	valids[0x1]	258	1			T55	4		T56	4		T45	2
auto[1]	values[6]	valids[0x0]	404	1			T55	4		T97	2		T56	3
auto[1]	values[6]	valids[0x1]	265	1			T55	5		T56	3		T45	3
auto[1]	values[7]	valids[0x0]	319	1			T55	1		T56	3		T45	4
auto[1]	values[7]	valids[0x1]	253	1			T55	1		T111	1		T224	1
auto[1]	values[8]	valids[0x0]	2538	1			T11	2		T57	1		T58	2
auto[1]	values[8]	valids[0x1]	1821	1			T55	31		T94	1		T97	2