Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3217974

1

T7

1

T8

100

T9

962

auto[1]

29475

1

T55

193

T56

206

T45

25

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

807766

1

T7

1

T8

100

T9

404

auto[1]

2439683

1

T9

558

T19

10026

T38

5108

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	677036	1			T7	1		T8	15		T9	681
auto[524288:1048575]	350825	1			T19	461		T225	608		T67	7
auto[1048576:1572863]	359942	1			T9	3		T19	711		T20	89
auto[1572864:2097151]	423232	1			T9	103		T18	412		T19	325
auto[2097152:2621439]	372267	1			T8	85		T11	36		T20	37
auto[2621440:3145727]	369423	1			T17	2		T20	23		T57	202
auto[3145728:3670015]	344502	1			T9	116		T11	1		T19	5671
auto[3670016:4194303]	350222	1			T9	59		T18	2		T20	7

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2472886

1

T7

1

T8

11

T9

573

auto[1]

774563

1

T8

89

T9

389

T11

486

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2803827

1

T7

1

T8

100

T9

962

auto[1]

443622

1

T55

5162

T94

1

T56

161

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	181032	1			T7	1		T8	15		T9	138
auto[0]	auto[0]	auto[0:524287]	auto[1]	432055	1			T9	543		T19	4882		T38	5108
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	72706	1			T19	461		T225	608		T67	7
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	200746	1			T55	258		T111	956		T266	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	110899	1			T9	3		T19	697		T20	89
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	181901	1			T19	14		T55	1548		T56	129
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	112753	1			T9	96		T18	412		T19	170
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	259486	1			T9	7		T19	155		T55	257
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	63273	1			T8	85		T11	36		T20	37
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	253150	1			T55	512		T56	265		T111	726
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	100115	1			T17	2		T20	23		T57	202
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	221421	1			T55	6183		T94	220		T56	365
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	76704	1			T9	109		T11	1		T19	696
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	216834	1			T9	7		T19	4975		T55	332
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	77967	1			T9	58		T18	2		T20	7
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	218846	1			T9	1		T117	17		T63	5447
auto[0]	auto[1]	auto[0:524287]	auto[0]	642	1			T55	1		T94	1		T111	7
auto[0]	auto[1]	auto[0:524287]	auto[1]	59229	1			T72	1		T77	138		T211	3
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1352	1			T45	4		T111	30		T112	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	72374	1			T45	834		T112	1013		T217	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	852	1			T56	2		T112	1		T51	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	63443	1			T219	128		T125	1		T386	384
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1739	1			T56	1		T63	6		T88	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	45845	1			T56	128		T63	1250		T129	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	977	1			T55	2		T63	1		T112	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	51225	1			T55	256		T112	512		T129	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	988	1			T55	6		T56	1		T45	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	43733	1			T55	4583		T56	1		T211	5654
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1051	1			T55	1		T45	1		T280	300
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	44859	1			T55	256		T45	1		T211	128
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1003	1			T72	1		T112	1		T129	9
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	48774	1			T129	1485		T215	513		T144	2822
auto[1]	auto[0]	auto[0:524287]	auto[0]	537	1			T55	2		T56	2		T111	6
auto[1]	auto[0]	auto[0:524287]	auto[1]	2627	1			T55	9		T56	24		T63	70
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	346	1			T55	2		T113	9		T129	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2427	1			T55	85		T113	13		T129	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	286	1			T55	2		T56	1		T63	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1901	1			T55	10		T56	11		T63	10
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	370	1			T55	1		T56	5		T111	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2264	1			T55	21		T56	117		T63	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	459	1			T56	2		T112	1		T73	22
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2724	1			T56	16		T112	5		T73	109
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	365	1			T45	1		T111	5		T72	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2052	1			T45	12		T72	7		T129	8
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	415	1			T55	1		T45	1		T111	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	4130	1			T55	3		T45	4		T111	255
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	309	1			T63	1		T72	2		T112	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2727	1			T63	15		T72	11		T112	6
auto[1]	auto[1]	auto[0:524287]	auto[0]	110	1			T72	1		T77	1		T211	3
auto[1]	auto[1]	auto[0:524287]	auto[1]	804	1			T72	4		T77	1		T211	14
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	78	1			T45	2		T220	1		T386	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	796	1			T45	3		T220	31		T386	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	61	1			T125	1		T232	4		T374	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	599	1			T125	22		T374	4		T228	11
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	79	1			T129	2		T212	1		T125	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	696	1			T129	21		T125	34		T139	256
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	80	1			T220	1		T139	3		T248	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	379	1			T220	53		T387	143		T248	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	63	1			T55	3		T56	1		T125	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	686	1			T55	54		T56	27		T125	43
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	67	1			T45	1		T40	2		T220	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	442	1			T45	1		T40	2		T220	36
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	88	1			T129	5		T217	7		T215	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	508	1			T129	69		T215	4		T52	69

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2010249	1			T7	1		T8	11		T9	573
auto[0]	auto[0]	auto[1]	769639	1			T8	89		T9	389		T11	486
auto[0]	auto[1]	auto[0]	433802	1			T55	5104		T94	1		T56	133
auto[0]	auto[1]	auto[1]	4284	1			T55	1		T280	607		T129	5
auto[1]	auto[0]	auto[0]	23410	1			T55	135		T56	177		T45	18
auto[1]	auto[0]	auto[1]	529	1			T55	1		T56	1		T111	3
auto[1]	auto[1]	auto[0]	5425	1			T55	56		T56	28		T45	7
auto[1]	auto[1]	auto[1]	111	1			T55	1		T129	1		T217	1