Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2612242	1			T1	1		T2	1		T4	1
all_pins[1]	2612242	1			T1	1		T2	1		T4	1
all_pins[2]	2612242	1			T1	1		T2	1		T4	1
all_pins[3]	2612242	1			T1	1		T2	1		T4	1
all_pins[4]	2612242	1			T1	1		T2	1		T4	1
all_pins[5]	2612242	1			T1	1		T2	1		T4	1
all_pins[6]	2612242	1			T1	1		T2	1		T4	1
all_pins[7]	2612242	1			T1	1		T2	1		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20844214	1			T1	8		T2	8		T4	8
values[0x1]	53722	1			T14	22		T21	5		T34	17
transitions[0x0=>0x1]	52367	1			T14	18		T21	4		T34	12
transitions[0x1=>0x0]	52378	1			T14	18		T21	4		T34	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2611579	1			T1	1		T2	1		T4	1
all_pins[0]	values[0x1]	663	1			T14	3		T21	1		T34	3
all_pins[0]	transitions[0x0=>0x1]	281	1			T14	3		T21	1		T34	3
all_pins[0]	transitions[0x1=>0x0]	306	1			T14	3		T51	1		T77	3
all_pins[1]	values[0x0]	2611554	1			T1	1		T2	1		T4	1
all_pins[1]	values[0x1]	688	1			T14	3		T51	1		T77	4
all_pins[1]	transitions[0x0=>0x1]	523	1			T14	2		T51	1		T77	3
all_pins[1]	transitions[0x1=>0x0]	138	1			T14	3		T34	3		T36	2
all_pins[2]	values[0x0]	2611939	1			T1	1		T2	1		T4	1
all_pins[2]	values[0x1]	303	1			T14	4		T34	3		T36	2
all_pins[2]	transitions[0x0=>0x1]	261	1			T14	4		T34	2		T36	2
all_pins[2]	transitions[0x1=>0x0]	126	1			T14	2		T21	1		T51	2
all_pins[3]	values[0x0]	2612074	1			T1	1		T2	1		T4	1
all_pins[3]	values[0x1]	168	1			T14	2		T21	1		T34	1
all_pins[3]	transitions[0x0=>0x1]	125	1			T14	2		T21	1		T77	5
all_pins[3]	transitions[0x1=>0x0]	132	1			T34	2		T51	4		T77	4
all_pins[4]	values[0x0]	2612067	1			T1	1		T2	1		T4	1
all_pins[4]	values[0x1]	175	1			T34	3		T51	6		T77	5
all_pins[4]	transitions[0x0=>0x1]	134	1			T34	3		T51	4		T77	4
all_pins[4]	transitions[0x1=>0x0]	1239	1			T14	6		T21	2		T34	1
all_pins[5]	values[0x0]	2610962	1			T1	1		T2	1		T4	1
all_pins[5]	values[0x1]	1280	1			T14	6		T21	2		T34	1
all_pins[5]	transitions[0x0=>0x1]	690	1			T14	4		T21	1		T51	1
all_pins[5]	transitions[0x1=>0x0]	49678	1			T14	1		T34	4		T36	4
all_pins[6]	values[0x0]	2561974	1			T1	1		T2	1		T4	1
all_pins[6]	values[0x1]	50268	1			T14	3		T21	1		T34	5
all_pins[6]	transitions[0x0=>0x1]	50224	1			T14	2		T21	1		T34	4
all_pins[6]	transitions[0x1=>0x0]	133	1			T51	3		T77	4		T204	2
all_pins[7]	values[0x0]	2612065	1			T1	1		T2	1		T4	1
all_pins[7]	values[0x1]	177	1			T14	1		T34	1		T36	1
all_pins[7]	transitions[0x0=>0x1]	129	1			T14	1		T36	1		T51	2
all_pins[7]	transitions[0x1=>0x0]	626	1			T14	3		T21	1		T34	2