Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15849

1

T9

8

T12

6

T17

2

auto[1]

12528

1

T7

16

T54

6

T68

4

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3714	1			T18	2		T19	8		T66	12
values[1]	3475	1			T117	14		T63	31		T271	18
values[2]	3428	1			T9	8		T68	4		T65	12
values[3]	3767	1			T17	2		T142	18		T60	8
values[4]	3328	1			T38	22		T59	10		T61	12
values[5]	3399	1			T7	16		T12	6		T49	14
values[6]	3520	1			T20	6		T63	20		T88	20
values[7]	3746	1			T54	6		T95	14		T62	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2833	1			T12	6		T142	18		T70	24
values[1]	3654	1			T9	8		T20	6		T67	12
values[2]	3464	1			T19	8		T59	10		T225	4
values[3]	3731	1			T54	6		T49	14		T68	4
values[4]	3557	1			T7	16		T17	2		T18	2
values[5]	3802	1			T38	22		T61	12		T65	12
values[6]	3448	1			T66	12		T92	6		T63	99
values[7]	3888	1			T93	10		T63	20		T84	10

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	233	1			T74	22		T248	25		T254	8
auto[0]	values[0]	values[1]	245	1			T215	12		T237	25		T388	33
auto[0]	values[0]	values[2]	265	1			T19	8		T51	21		T214	10
auto[0]	values[0]	values[3]	171	1			T77	8		T306	11		T254	11
auto[0]	values[0]	values[4]	346	1			T18	2		T63	27		T217	12
auto[0]	values[0]	values[5]	189	1			T63	10		T115	8		T241	14
auto[0]	values[0]	values[6]	433	1			T66	12		T63	92		T71	113
auto[0]	values[0]	values[7]	372	1			T232	10		T242	16		T333	19
auto[0]	values[1]	values[0]	165	1			T73	9		T373	8		T232	15
auto[0]	values[1]	values[1]	531	1			T271	18		T222	8		T264	4
auto[0]	values[1]	values[2]	283	1			T273	2		T283	6		T276	6
auto[0]	values[1]	values[3]	214	1			T211	10		T242	13		T228	10
auto[0]	values[1]	values[4]	237	1			T63	26		T230	8		T284	14
auto[0]	values[1]	values[5]	374	1			T117	14		T226	6		T232	13
auto[0]	values[1]	values[6]	216	1			T260	8		T243	14		T215	26
auto[0]	values[1]	values[7]	148	1			T73	8		T217	13		T227	8
auto[0]	values[2]	values[0]	111	1			T252	8		T242	12		T306	11
auto[0]	values[2]	values[1]	291	1			T9	8		T231	4		T389	41
auto[0]	values[2]	values[2]	135	1			T286	16		T390	2		T318	8
auto[0]	values[2]	values[3]	226	1			T213	13		T242	18		T254	10
auto[0]	values[2]	values[4]	264	1			T85	16		T246	10		T137	2
auto[0]	values[2]	values[5]	206	1			T237	16		T362	18		T324	28
auto[0]	values[2]	values[6]	279	1			T88	12		T211	12		T232	10
auto[0]	values[2]	values[7]	244	1			T84	10		T277	2		T228	52
auto[0]	values[3]	values[0]	327	1			T142	18		T238	6		T275	6
auto[0]	values[3]	values[1]	170	1			T67	12		T73	10		T215	9
auto[0]	values[3]	values[2]	168	1			T72	25		T306	9		T248	8
auto[0]	values[3]	values[3]	272	1			T73	14		T305	11		T228	19
auto[0]	values[3]	values[4]	248	1			T17	2		T60	8		T237	23
auto[0]	values[3]	values[5]	284	1			T269	12		T214	29		T242	13
auto[0]	values[3]	values[6]	302	1			T92	6		T72	24		T259	10
auto[0]	values[3]	values[7]	342	1			T234	8		T284	20		T312	14
auto[0]	values[4]	values[0]	176	1			T285	8		T228	58		T299	9
auto[0]	values[4]	values[1]	242	1			T81	2		T232	12		T254	50
auto[0]	values[4]	values[2]	252	1			T59	10		T280	2		T232	10
auto[0]	values[4]	values[3]	160	1			T51	12		T391	2		T251	13
auto[0]	values[4]	values[4]	125	1			T247	6		T72	10		T335	15
auto[0]	values[4]	values[5]	279	1			T38	22		T61	12		T215	11
auto[0]	values[4]	values[6]	143	1			T223	14		T77	11		T322	9
auto[0]	values[4]	values[7]	243	1			T216	28		T228	9		T392	12
auto[0]	values[5]	values[0]	134	1			T12	6		T211	40		T237	25
auto[0]	values[5]	values[1]	275	1			T217	13		T232	12		T228	10
auto[0]	values[5]	values[2]	364	1			T225	4		T120	8		T229	4
auto[0]	values[5]	values[3]	260	1			T49	14		T266	6		T63	8
auto[0]	values[5]	values[4]	330	1			T143	13		T211	6		T265	24
auto[0]	values[5]	values[5]	185	1			T291	6		T393	2		T394	10
auto[0]	values[5]	values[6]	159	1			T73	16		T53	19		T313	11
auto[0]	values[5]	values[7]	294	1			T77	16		T211	16		T210	16
auto[0]	values[6]	values[0]	243	1			T51	10		T77	13		T212	22
auto[0]	values[6]	values[1]	164	1			T20	6		T258	8		T358	6
auto[0]	values[6]	values[2]	221	1			T211	7		T215	14		T53	20
auto[0]	values[6]	values[3]	195	1			T235	14		T53	10		T289	6
auto[0]	values[6]	values[4]	255	1			T88	11		T77	8		T214	12
auto[0]	values[6]	values[5]	430	1			T214	13		T53	35		T213	59
auto[0]	values[6]	values[6]	184	1			T73	9		T211	13		T214	9
auto[0]	values[6]	values[7]	210	1			T63	12		T395	6		T250	23
auto[0]	values[7]	values[0]	215	1			T281	10		T212	5		T261	8
auto[0]	values[7]	values[1]	307	1			T87	10		T138	6		T214	12
auto[0]	values[7]	values[2]	290	1			T95	14		T62	12		T233	10
auto[0]	values[7]	values[3]	356	1			T279	2		T214	9		T53	16
auto[0]	values[7]	values[4]	236	1			T143	12		T214	14		T53	16
auto[0]	values[7]	values[5]	199	1			T263	6		T239	8		T210	9
auto[0]	values[7]	values[6]	222	1			T73	13		T362	3		T284	10
auto[0]	values[7]	values[7]	210	1			T53	11		T396	14		T397	4
auto[1]	values[0]	values[0]	89	1			T245	8		T248	7		T254	12
auto[1]	values[0]	values[1]	150	1			T215	13		T237	6		T295	10
auto[1]	values[0]	values[2]	329	1			T69	8		T51	8		T214	10
auto[1]	values[0]	values[3]	240	1			T64	24		T77	12		T306	9
auto[1]	values[0]	values[4]	200	1			T63	9		T217	8		T320	12
auto[1]	values[0]	values[5]	163	1			T63	10		T115	12		T213	6
auto[1]	values[0]	values[6]	75	1			T63	7		T228	5		T251	7
auto[1]	values[0]	values[7]	214	1			T232	10		T242	4		T333	7
auto[1]	values[1]	values[0]	137	1			T75	16		T73	11		T232	5
auto[1]	values[1]	values[1]	179	1			T211	11		T215	10		T210	10
auto[1]	values[1]	values[2]	150	1			T53	15		T254	6		T310	14
auto[1]	values[1]	values[3]	104	1			T211	10		T242	9		T228	10
auto[1]	values[1]	values[4]	122	1			T63	5		T284	6		T398	47
auto[1]	values[1]	values[5]	303	1			T232	7		T321	85		T322	6
auto[1]	values[1]	values[6]	150	1			T215	20		T237	5		T343	22
auto[1]	values[1]	values[7]	162	1			T73	12		T217	7		T214	36
auto[1]	values[2]	values[0]	81	1			T242	10		T306	11		T98	8
auto[1]	values[2]	values[1]	167	1			T248	59		T362	7		T326	8
auto[1]	values[2]	values[2]	106	1			T318	12		T99	11		T323	9
auto[1]	values[2]	values[3]	312	1			T68	4		T213	32		T242	8
auto[1]	values[2]	values[4]	225	1			T212	9		T242	9		T210	8
auto[1]	values[2]	values[5]	201	1			T65	12		T237	4		T362	6
auto[1]	values[2]	values[6]	178	1			T88	8		T211	10		T80	6
auto[1]	values[2]	values[7]	402	1			T228	93		T306	5		T237	8
auto[1]	values[3]	values[0]	338	1			T53	9		T210	156		T254	10
auto[1]	values[3]	values[1]	132	1			T73	10		T215	11		T242	9
auto[1]	values[3]	values[2]	142	1			T72	6		T306	11		T248	15
auto[1]	values[3]	values[3]	246	1			T73	6		T305	9		T228	21
auto[1]	values[3]	values[4]	145	1			T237	23		T326	3		T307	10
auto[1]	values[3]	values[5]	225	1			T214	11		T242	13		T237	9
auto[1]	values[3]	values[6]	249	1			T72	9		T254	9		T313	8
auto[1]	values[3]	values[7]	177	1			T284	20		T312	6		T207	9
auto[1]	values[4]	values[0]	114	1			T228	9		T299	11		T109	12
auto[1]	values[4]	values[1]	233	1			T232	8		T254	5		T237	32
auto[1]	values[4]	values[2]	199	1			T232	10		T322	113		T98	5
auto[1]	values[4]	values[3]	200	1			T51	8		T251	8		T326	75
auto[1]	values[4]	values[4]	160	1			T72	47		T76	14		T78	16
auto[1]	values[4]	values[5]	205	1			T215	9		T228	14		T248	10
auto[1]	values[4]	values[6]	286	1			T77	11		T322	122		T251	8
auto[1]	values[4]	values[7]	311	1			T93	10		T228	11		T306	10
auto[1]	values[5]	values[0]	155	1			T211	7		T288	24		T237	7
auto[1]	values[5]	values[1]	191	1			T217	7		T232	8		T228	54
auto[1]	values[5]	values[2]	149	1			T210	5		T237	7		T295	6
auto[1]	values[5]	values[3]	375	1			T63	12		T305	7		T228	12
auto[1]	values[5]	values[4]	197	1			T7	16		T143	7		T211	27
auto[1]	values[5]	values[5]	86	1			T399	2		T206	3		T329	14
auto[1]	values[5]	values[6]	121	1			T73	4		T53	60		T313	9
auto[1]	values[5]	values[7]	124	1			T77	4		T211	4		T210	4
auto[1]	values[6]	values[0]	200	1			T51	10		T77	11		T212	2
auto[1]	values[6]	values[1]	160	1			T282	20		T251	18		T313	7
auto[1]	values[6]	values[2]	231	1			T211	22		T215	6		T53	11
auto[1]	values[6]	values[3]	232	1			T53	32		T210	32		T254	11
auto[1]	values[6]	values[4]	193	1			T88	9		T77	28		T214	8
auto[1]	values[6]	values[5]	258	1			T214	7		T53	8		T213	28
auto[1]	values[6]	values[6]	154	1			T73	11		T211	13		T214	27
auto[1]	values[6]	values[7]	190	1			T63	8		T250	17		T284	7
auto[1]	values[7]	values[0]	115	1			T70	24		T212	15		T79	12
auto[1]	values[7]	values[1]	217	1			T214	70		T305	6		T335	7
auto[1]	values[7]	values[2]	180	1			T77	11		T109	9		T318	10
auto[1]	values[7]	values[3]	168	1			T54	6		T214	32		T53	5
auto[1]	values[7]	values[4]	274	1			T143	8		T214	6		T53	4
auto[1]	values[7]	values[5]	215	1			T210	33		T306	5		T341	16
auto[1]	values[7]	values[6]	297	1			T73	7		T362	17		T284	123
auto[1]	values[7]	values[7]	245	1			T53	9		T315	11		T98	12