Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	366	1			T92	4		T63	3		T226	6
auto[ReadAddrCrossIntoMailbox]	274	1			T63	4		T87	4		T115	2
auto[ReadAddrCrossOutOfMailbox]	273	1			T63	5		T87	4		T88	1
auto[ReadAddrCrossAllMailbox]	197	1			T63	3		T87	2		T72	1
auto[ReadAddrOutsideMailbox]	3356	1			T7	2		T9	2		T54	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2266

1

T7

1

T9

1

T54

2

auto[1]

2200

1

T7

1

T9

1

T54

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	760	1			T54	2		T59	4		T66	2
read_ops[0x0b]	753	1			T54	2		T64	4		T92	4
read_ops[0x3b]	687	1			T64	6		T63	3		T88	1
read_ops[0x6b]	803	1			T9	2		T49	2		T93	4
read_ops[0xbb]	722	1			T7	2		T59	2		T64	2
read_ops[0xeb]	741	1			T38	2		T61	2		T62	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T63	1		T226	2		T73	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T226	2		T143	1		T213	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T63	1		T258	1		T211	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T51	1		T258	1		T214	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T63	2		T87	1		T88	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T87	1		T51	1		T214	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T72	1		T305	1		T210	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T213	1		T400	2		T336	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	266	1			T54	1		T59	2		T66	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	270	1			T54	1		T59	2		T66	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T92	2		T291	1		T401	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T92	2		T143	1		T291	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T235	1		T214	1		T305	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T215	1		T235	1		T53	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T217	1		T254	2		T313	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T63	1		T72	1		T215	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T235	2		T214	1		T213	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T215	3		T235	2		T232	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	271	1			T54	1		T64	2		T65	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	303	1			T54	1		T64	2		T65	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T63	1		T211	1		T210	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T232	1		T248	1		T237	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T215	1		T390	1		T214	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T390	1		T242	1		T228	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	13	1			T211	1		T228	1		T359	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T72	1		T232	1		T242	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T217	1		T237	2		T400	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T228	1		T248	1		T400	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	267	1			T64	3		T63	2		T88	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	259	1			T64	3		T72	1		T231	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T226	1		T51	1		T273	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	18	1			T226	1		T51	1		T273	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T87	1		T115	1		T73	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	15	1			T63	1		T87	1		T51	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T87	1		T217	1		T53	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T87	1		T214	1		T232	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T63	1		T87	1		T258	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T63	1		T87	1		T258	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	325	1			T9	1		T49	1		T93	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T9	1		T49	1		T93	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T77	1		T305	1		T210	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T63	1		T232	1		T242	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T63	2		T87	1		T115	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T87	1		T214	1		T53	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T63	1		T53	1		T402	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T214	1		T232	1		T242	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T228	2		T248	3		T254	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T214	1		T322	1		T327	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	275	1			T7	1		T59	1		T64	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	270	1			T7	1		T59	1		T64	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T214	2		T248	1		T383	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T72	1		T53	1		T210	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T215	1		T214	1		T53	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T232	2		T210	1		T306	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T53	1		T305	1		T248	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T63	1		T210	1		T383	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T63	1		T73	1		T211	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T143	1		T215	1		T214	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	269	1			T38	1		T61	1		T62	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T38	1		T61	1		T62	2