Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3175	1			T142	18		T81	2		T69	8
values[1]	3340	1			T54	6		T38	22		T225	4
values[2]	3344	1			T66	12		T95	14		T117	14
values[3]	3387	1			T9	8		T17	2		T67	12
values[4]	4074	1			T12	6		T18	2		T19	8
values[5]	3371	1			T7	16		T63	56		T71	113
values[6]	3473	1			T49	14		T68	4		T64	24
values[7]	4213	1			T59	10		T61	12		T92	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2903	1			T49	14		T92	6		T226	6
values[1]	4528	1			T19	8		T68	4		T225	4
values[2]	3259	1			T12	6		T20	6		T142	18
values[3]	4137	1			T9	8		T59	10		T60	8
values[4]	3597	1			T17	2		T18	2		T54	6
values[5]	2979	1			T67	12		T66	12		T88	20
values[6]	3357	1			T7	16		T64	24		T120	8
values[7]	3617	1			T61	12		T81	2		T71	113

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27654

1

T7

16

T9

8

T12

6

auto[1]

723

1

T63

1

T69

2

T70

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[5]]	[values[2]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	418	1			T51	16		T227	8		T228	39
auto[0]	values[0]	values[1]	273	1			T215	25		T229	4		T230	8
auto[0]	values[0]	values[2]	400	1			T142	18		T231	4		T232	39
auto[0]	values[0]	values[3]	521	1			T69	6		T233	10		T234	8
auto[0]	values[0]	values[4]	347	1			T235	14		T213	45		T210	20
auto[0]	values[0]	values[5]	434	1			T72	33		T236	4		T237	20
auto[0]	values[0]	values[6]	284	1			T238	6		T239	8		T240	4
auto[0]	values[0]	values[7]	404	1			T81	2		T211	33		T215	21
auto[0]	values[1]	values[0]	356	1			T215	20		T241	14		T242	20
auto[0]	values[1]	values[1]	432	1			T225	4		T63	20		T213	18
auto[0]	values[1]	values[2]	476	1			T243	14		T244	14		T245	6
auto[0]	values[1]	values[3]	503	1			T60	8		T246	10		T53	31
auto[0]	values[1]	values[4]	477	1			T54	6		T38	22		T247	6
auto[0]	values[1]	values[5]	301	1			T215	20		T228	64		T248	20
auto[0]	values[1]	values[6]	466	1			T211	46		T80	4		T249	4
auto[0]	values[1]	values[7]	243	1			T79	10		T250	20		T251	27
auto[0]	values[2]	values[0]	340	1			T226	6		T73	20		T252	8
auto[0]	values[2]	values[1]	484	1			T253	12		T254	20		T255	4
auto[0]	values[2]	values[2]	388	1			T213	22		T256	10		T257	4
auto[0]	values[2]	values[3]	614	1			T117	14		T211	24		T138	6
auto[0]	values[2]	values[4]	297	1			T95	14		T143	20		T258	8
auto[0]	values[2]	values[5]	223	1			T66	12		T215	20		T53	20
auto[0]	values[2]	values[6]	325	1			T77	24		T259	10		T254	55
auto[0]	values[2]	values[7]	593	1			T260	8		T214	36		T53	56
auto[0]	values[3]	values[0]	373	1			T261	8		T254	20		T262	16
auto[0]	values[3]	values[1]	630	1			T118	12		T263	6		T73	20
auto[0]	values[3]	values[2]	362	1			T222	8		T217	20		T53	42
auto[0]	values[3]	values[3]	341	1			T9	8		T62	12		T214	19
auto[0]	values[3]	values[4]	391	1			T17	2		T264	4		T265	24
auto[0]	values[3]	values[5]	489	1			T67	12		T88	20		T214	20
auto[0]	values[3]	values[6]	303	1			T266	6		T232	20		T267	24
auto[0]	values[3]	values[7]	411	1			T211	22		T212	20		T53	19
auto[0]	values[4]	values[0]	402	1			T77	20		T211	20		T268	12
auto[0]	values[4]	values[1]	838	1			T19	8		T72	56		T75	12
auto[0]	values[4]	values[2]	246	1			T12	6		T20	6		T217	16
auto[0]	values[4]	values[3]	459	1			T51	20		T269	12		T270	8
auto[0]	values[4]	values[4]	648	1			T18	2		T63	98		T88	20
auto[0]	values[4]	values[5]	364	1			T271	18		T272	4		T232	19
auto[0]	values[4]	values[6]	711	1			T120	8		T74	22		T77	18
auto[0]	values[4]	values[7]	286	1			T273	2		T213	26		T274	6
auto[0]	values[5]	values[0]	366	1			T72	29		T73	20		T275	6
auto[0]	values[5]	values[1]	351	1			T63	36		T276	6		T53	39
auto[0]	values[5]	values[2]	277	1			T63	20		T277	2		T278	18
auto[0]	values[5]	values[3]	549	1			T73	38		T232	20		T250	19
auto[0]	values[5]	values[4]	407	1			T279	2		T280	2		T281	10
auto[0]	values[5]	values[5]	459	1			T115	20		T282	20		T242	20
auto[0]	values[5]	values[6]	260	1			T7	16		T211	20		T237	20
auto[0]	values[5]	values[7]	630	1			T71	113		T143	20		T283	6
auto[0]	values[6]	values[0]	344	1			T49	14		T228	64		T251	19
auto[0]	values[6]	values[1]	360	1			T68	4		T84	10		T85	16
auto[0]	values[6]	values[2]	550	1			T73	18		T214	39		T284	20
auto[0]	values[6]	values[3]	473	1			T63	31		T217	20		T210	20
auto[0]	values[6]	values[4]	418	1			T70	18		T76	12		T228	20
auto[0]	values[6]	values[5]	259	1			T216	28		T285	8		T228	20
auto[0]	values[6]	values[6]	420	1			T64	24		T63	20		T286	16
auto[0]	values[6]	values[7]	563	1			T215	23		T213	63		T287	14
auto[0]	values[7]	values[0]	230	1			T92	6		T223	14		T137	2
auto[0]	values[7]	values[1]	1055	1			T214	39		T228	49		T288	24
auto[0]	values[7]	values[2]	468	1			T93	10		T214	45		T232	40
auto[0]	values[7]	values[3]	573	1			T59	10		T210	92		T254	20
auto[0]	values[7]	values[4]	515	1			T65	12		T77	22		T211	29
auto[0]	values[7]	values[5]	376	1			T214	18		T289	6		T290	2
auto[0]	values[7]	values[6]	500	1			T291	6		T212	23		T242	25
auto[0]	values[7]	values[7]	398	1			T61	12		T87	10		T77	34
auto[1]	values[0]	values[0]	11	1			T51	4		T228	2		T292	1
auto[1]	values[0]	values[1]	11	1			T228	4		T293	2		T294	1
auto[1]	values[0]	values[2]	17	1			T232	1		T251	1		T295	1
auto[1]	values[0]	values[3]	19	1			T69	2		T254	2		T295	1
auto[1]	values[0]	values[4]	5	1			T251	2		T296	3		-	-
auto[1]	values[0]	values[5]	7	1			T206	2		T297	3		T298	2
auto[1]	values[0]	values[6]	8	1			T299	2		T300	2		T301	1
auto[1]	values[0]	values[7]	16	1			T210	1		T109	1		T302	1
auto[1]	values[1]	values[0]	4	1			T99	1		T303	1		T304	1
auto[1]	values[1]	values[1]	10	1			T213	2		T305	3		T306	2
auto[1]	values[1]	values[2]	15	1			T245	2		T237	1		T284	2
auto[1]	values[1]	values[3]	16	1			T307	1		T302	3		T308	1
auto[1]	values[1]	values[4]	15	1			T73	1		T78	2		T53	1
auto[1]	values[1]	values[5]	7	1			T237	2		T99	1		T309	3
auto[1]	values[1]	values[6]	13	1			T211	1		T80	2		T306	2
auto[1]	values[1]	values[7]	6	1			T79	2		T251	1		T284	1
auto[1]	values[2]	values[0]	7	1			T310	2		T311	1		T187	1
auto[1]	values[2]	values[1]	7	1			T295	1		T98	2		T109	1
auto[1]	values[2]	values[2]	17	1			T213	2		T98	2		T312	2
auto[1]	values[2]	values[3]	23	1			T211	2		T313	1		T206	5
auto[1]	values[2]	values[4]	6	1			T305	1		T250	1		T314	2
auto[1]	values[2]	values[5]	4	1			T109	3		T207	1		-	-
auto[1]	values[2]	values[6]	9	1			T284	2		T315	2		T311	4
auto[1]	values[2]	values[7]	7	1			T53	3		T316	1		T317	2
auto[1]	values[3]	values[0]	16	1			T262	4		T318	3		T319	1
auto[1]	values[3]	values[1]	17	1			T320	2		T242	3		T228	2
auto[1]	values[3]	values[2]	9	1			T321	1		T322	1		T284	3
auto[1]	values[3]	values[3]	9	1			T214	1		T318	1		T314	1
auto[1]	values[3]	values[4]	12	1			T232	5		T323	1		T319	2
auto[1]	values[3]	values[5]	8	1			T324	1		T207	2		T325	1
auto[1]	values[3]	values[6]	7	1			T250	2		T326	3		T327	1
auto[1]	values[3]	values[7]	9	1			T53	1		T315	2		T308	2
auto[1]	values[4]	values[0]	14	1			T251	1		T326	1		T99	1
auto[1]	values[4]	values[1]	30	1			T72	1		T75	4		T211	3
auto[1]	values[4]	values[2]	10	1			T217	4		T328	2		T329	1
auto[1]	values[4]	values[3]	10	1			T322	2		T330	1		T331	1
auto[1]	values[4]	values[4]	21	1			T63	1		T232	3		T248	2
auto[1]	values[4]	values[5]	10	1			T232	1		T326	2		T300	2
auto[1]	values[4]	values[6]	21	1			T77	2		T322	4		T324	3
auto[1]	values[4]	values[7]	4	1			T242	1		T327	1		T332	2
auto[1]	values[5]	values[0]	8	1			T72	2		T210	2		T248	2
auto[1]	values[5]	values[1]	3	1			T322	1		T312	1		T333	1
auto[1]	values[5]	values[3]	13	1			T73	2		T250	1		T307	2
auto[1]	values[5]	values[4]	15	1			T330	2		T311	3		T323	3
auto[1]	values[5]	values[5]	15	1			T322	2		T206	1		T302	1
auto[1]	values[5]	values[6]	1	1			T334	1		-	-		-	-
auto[1]	values[5]	values[7]	17	1			T254	1		T335	1		T336	1
auto[1]	values[6]	values[0]	13	1			T228	3		T251	1		T314	1
auto[1]	values[6]	values[1]	8	1			T77	1		T210	1		T335	1
auto[1]	values[6]	values[2]	14	1			T73	2		T214	1		T318	1
auto[1]	values[6]	values[3]	6	1			T337	1		T338	1		T339	1
auto[1]	values[6]	values[4]	17	1			T70	6		T76	2		T335	1
auto[1]	values[6]	values[5]	4	1			T336	2		T324	1		T325	1
auto[1]	values[6]	values[6]	6	1			T212	1		T284	2		T324	1
auto[1]	values[6]	values[7]	18	1			T215	2		T109	1		T316	4
auto[1]	values[7]	values[0]	1	1			T308	1		-	-		-	-
auto[1]	values[7]	values[1]	19	1			T214	2		T340	4		T333	1
auto[1]	values[7]	values[2]	10	1			T254	2		T294	2		T101	2
auto[1]	values[7]	values[3]	8	1			T210	1		T308	1		T303	2
auto[1]	values[7]	values[4]	6	1			T341	4		T250	1		T342	1
auto[1]	values[7]	values[5]	19	1			T214	2		T336	1		T99	1
auto[1]	values[7]	values[6]	23	1			T212	1		T242	1		T343	2
auto[1]	values[7]	values[7]	12	1			T77	2		T228	2		T327	2