Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	763	1			T14	15		T21	4		T34	7
all_values[1]	763	1			T14	15		T21	4		T34	7
all_values[2]	763	1			T14	15		T21	4		T34	7
all_values[3]	763	1			T14	15		T21	4		T34	7
all_values[4]	763	1			T14	15		T21	4		T34	7
all_values[5]	763	1			T14	15		T21	4		T34	7
all_values[6]	763	1			T14	15		T21	4		T34	7
all_values[7]	763	1			T14	15		T21	4		T34	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3204

1

T14

54

T21

24

T34

28

auto[1]

2900

1

T14

66

T21

8

T34

28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2461

1

T14

62

T21

14

T34

19

auto[1]

3643

1

T14

58

T21

18

T34

37

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3476

1

T14

83

T21

20

T34

34

auto[1]

2628

1

T14

37

T21

12

T34

22

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	153	1			T14	3		T34	2		T36	1
all_values[0]	auto[0]	auto[0]	auto[1]	64	1			T14	1		T34	1		T77	2
all_values[0]	auto[0]	auto[1]	auto[0]	157	1			T14	8		T21	2		T51	2
all_values[0]	auto[0]	auto[1]	auto[1]	72	1			T34	1		T36	1		T51	2
all_values[0]	auto[1]	auto[0]	auto[1]	156	1			T14	1		T21	2		T34	1
all_values[0]	auto[1]	auto[1]	auto[1]	161	1			T14	2		T34	2		T36	1
all_values[1]	auto[0]	auto[0]	auto[0]	173	1			T14	2		T21	2		T34	1
all_values[1]	auto[0]	auto[0]	auto[1]	73	1			T14	5		T34	2		T77	1
all_values[1]	auto[0]	auto[1]	auto[0]	133	1			T21	1		T34	2		T36	4
all_values[1]	auto[0]	auto[1]	auto[1]	70	1			T14	3		T77	2		T210	2
all_values[1]	auto[1]	auto[0]	auto[1]	173	1			T14	4		T21	1		T34	1
all_values[1]	auto[1]	auto[1]	auto[1]	141	1			T14	1		T34	1		T51	1
all_values[2]	auto[0]	auto[0]	auto[0]	151	1			T14	4		T21	1		T34	1
all_values[2]	auto[0]	auto[0]	auto[1]	84	1			T14	3		T21	1		T34	2
all_values[2]	auto[0]	auto[1]	auto[0]	126	1			T14	1		T36	3		T51	2
all_values[2]	auto[0]	auto[1]	auto[1]	66	1			T14	1		T34	1		T36	1
all_values[2]	auto[1]	auto[0]	auto[1]	200	1			T14	3		T21	2		T34	1
all_values[2]	auto[1]	auto[1]	auto[1]	136	1			T14	3		T34	2		T51	2
all_values[3]	auto[0]	auto[0]	auto[0]	146	1			T14	4		T21	3		T34	3
all_values[3]	auto[0]	auto[0]	auto[1]	80	1			T36	1		T51	2		T77	2
all_values[3]	auto[0]	auto[1]	auto[0]	121	1			T14	5		T34	1		T36	2
all_values[3]	auto[0]	auto[1]	auto[1]	69	1			T14	1		T51	1		T77	2
all_values[3]	auto[1]	auto[0]	auto[1]	190	1			T14	3		T34	1		T36	1
all_values[3]	auto[1]	auto[1]	auto[1]	157	1			T14	2		T21	1		T34	2
all_values[4]	auto[0]	auto[0]	auto[0]	153	1			T14	3		T21	1		T34	1
all_values[4]	auto[0]	auto[0]	auto[1]	71	1			T14	1		T21	2		T34	2
all_values[4]	auto[0]	auto[1]	auto[0]	137	1			T14	7		T51	1		T77	3
all_values[4]	auto[0]	auto[1]	auto[1]	68	1			T51	4		T77	1		T205	1
all_values[4]	auto[1]	auto[0]	auto[1]	173	1			T14	3		T21	1		T34	1
all_values[4]	auto[1]	auto[1]	auto[1]	161	1			T14	1		T34	3		T51	5
all_values[5]	auto[0]	auto[0]	auto[0]	228	1			T14	1		T21	1		T34	1
all_values[5]	auto[0]	auto[1]	auto[0]	207	1			T14	6		T21	1		T34	3
all_values[5]	auto[1]	auto[0]	auto[1]	174	1			T14	1		T34	2		T36	2
all_values[5]	auto[1]	auto[1]	auto[1]	154	1			T14	7		T21	2		T34	1
all_values[6]	auto[0]	auto[0]	auto[0]	150	1			T14	2		T34	1		T77	2
all_values[6]	auto[0]	auto[0]	auto[1]	58	1			T14	2		T21	1		T51	2
all_values[6]	auto[0]	auto[1]	auto[0]	141	1			T14	6		T51	3		T77	4
all_values[6]	auto[0]	auto[1]	auto[1]	92	1			T14	2		T21	1		T34	3
all_values[6]	auto[1]	auto[0]	auto[1]	161	1			T14	1		T21	2		T34	1
all_values[6]	auto[1]	auto[1]	auto[1]	161	1			T14	2		T34	2		T36	3
all_values[7]	auto[0]	auto[0]	auto[0]	159	1			T14	4		T21	2		T34	1
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T14	2		T21	1		T34	1
all_values[7]	auto[0]	auto[1]	auto[0]	126	1			T14	6		T34	2		T36	1
all_values[7]	auto[0]	auto[1]	auto[1]	71	1			T34	2		T51	2		T77	2
all_values[7]	auto[1]	auto[0]	auto[1]	157	1			T14	1		T21	1		T34	1
all_values[7]	auto[1]	auto[1]	auto[1]	173	1			T14	2		T36	2		T51	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal