Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1820

1

T4

9

T5

4

T10

1

auto[1]

1861

1

T4

3

T5

7

T10

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2025

1

T10

4

T26

1

T31

12

auto[1]

1656

1

T4

12

T5

11

T25

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2913

1

T4

12

T5

11

T10

1

auto[1]

768

1

T10

3

T31

3

T44

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	733	1			T4	2		T5	5		T26	1
valid[1]	758	1			T4	2		T5	1		T10	1
valid[2]	750	1			T4	1		T5	3		T10	2
valid[3]	707	1			T4	4		T28	5		T30	7
valid[4]	733	1			T4	3		T5	2		T10	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	136	1			T26	1		T31	1		T45	1
auto[0]	auto[0]	valid[0]	auto[1]	163	1			T4	1		T5	2		T28	2
auto[0]	auto[0]	valid[1]	auto[0]	134	1			T116	1		T134	1		T88	3
auto[0]	auto[0]	valid[1]	auto[1]	163	1			T4	2		T28	3		T30	2
auto[0]	auto[0]	valid[2]	auto[0]	150	1			T10	1		T31	1		T89	1
auto[0]	auto[0]	valid[2]	auto[1]	174	1			T5	1		T32	1		T28	4
auto[0]	auto[0]	valid[3]	auto[0]	102	1			T31	2		T116	1		T88	2
auto[0]	auto[0]	valid[3]	auto[1]	167	1			T4	3		T28	2		T30	5
auto[0]	auto[0]	valid[4]	auto[0]	121	1			T31	1		T116	1		T134	1
auto[0]	auto[0]	valid[4]	auto[1]	143	1			T4	3		T5	1		T25	1
auto[0]	auto[1]	valid[0]	auto[0]	117	1			T31	1		T45	1		T134	1
auto[0]	auto[1]	valid[0]	auto[1]	168	1			T4	1		T5	3		T28	2
auto[0]	auto[1]	valid[1]	auto[0]	127	1			T45	1		T116	1		T88	1
auto[0]	auto[1]	valid[1]	auto[1]	168	1			T5	1		T28	2		T30	5
auto[0]	auto[1]	valid[2]	auto[0]	120	1			T31	2		T88	2		T224	3
auto[0]	auto[1]	valid[2]	auto[1]	164	1			T4	1		T5	2		T28	3
auto[0]	auto[1]	valid[3]	auto[0]	119	1			T116	2		T88	1		T224	1
auto[0]	auto[1]	valid[3]	auto[1]	163	1			T4	1		T28	3		T30	2
auto[0]	auto[1]	valid[4]	auto[0]	131	1			T31	1		T44	2		T134	1
auto[0]	auto[1]	valid[4]	auto[1]	183	1			T5	1		T25	1		T28	2
auto[1]	auto[0]	valid[0]	auto[0]	73	1			T31	1		T72	1		T422	1
auto[1]	auto[0]	valid[1]	auto[0]	71	1			T224	1		T72	1		T424	1
auto[1]	auto[0]	valid[2]	auto[0]	61	1			T31	1		T116	1		T421	4
auto[1]	auto[0]	valid[3]	auto[0]	81	1			T44	2		T116	1		T83	1
auto[1]	auto[0]	valid[4]	auto[0]	81	1			T45	1		T88	1		T421	1
auto[1]	auto[1]	valid[0]	auto[0]	76	1			T116	1		T88	2		T224	2
auto[1]	auto[1]	valid[1]	auto[0]	95	1			T10	1		T45	1		T116	1
auto[1]	auto[1]	valid[2]	auto[0]	81	1			T10	1		T31	1		T44	1
auto[1]	auto[1]	valid[3]	auto[0]	75	1			T116	1		T88	2		T224	1
auto[1]	auto[1]	valid[4]	auto[0]	74	1			T10	1		T88	1		T224	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal