Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50390

1

T6

9

T10

104

T27

1

auto[1]

16852

1

T4

12

T5

125

T10

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49205

1

T4

12

T5

125

T6

5

auto[1]

18037

1

T6

4

T10

35

T26

14

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34655	1			T4	12		T5	66		T6	4
others[1]	5619	1			T5	10		T6	4		T10	5
others[2]	5650	1			T5	13		T6	1		T10	9
others[3]	6417	1			T5	14		T10	11		T26	3
interest[1]	3680	1			T5	5		T10	5		T26	2
interest[4]	22833	1			T4	12		T5	49		T6	2
interest[64]	11221	1			T5	17		T10	19		T26	14

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16615	1			T6	2		T10	40		T27	1
auto[0]	auto[0]	others[1]	2694	1			T6	2		T10	4		T26	2
auto[0]	auto[0]	others[2]	2665	1			T6	1		T10	4		T26	3
auto[0]	auto[0]	others[3]	3072	1			T10	6		T26	1		T29	1
auto[0]	auto[0]	interest[1]	1828	1			T10	2		T26	1		T31	7
auto[0]	auto[0]	interest[4]	10891	1			T6	1		T10	30		T27	1
auto[0]	auto[0]	interest[64]	5479	1			T10	13		T26	8		T29	1
auto[0]	auto[1]	others[0]	8801	1			T4	12		T5	66		T10	5
auto[0]	auto[1]	others[1]	1388	1			T5	10		T26	1		T28	26
auto[0]	auto[1]	others[2]	1439	1			T5	13		T10	1		T26	1
auto[0]	auto[1]	others[3]	1653	1			T5	14		T10	2		T28	42
auto[0]	auto[1]	interest[1]	837	1			T5	5		T26	1		T28	9
auto[0]	auto[1]	interest[4]	5895	1			T4	12		T5	49		T10	4
auto[0]	auto[1]	interest[64]	2734	1			T5	17		T10	2		T26	1
auto[1]	auto[0]	others[0]	9239	1			T6	2		T10	20		T26	4
auto[1]	auto[0]	others[1]	1537	1			T6	2		T10	1		T26	1
auto[1]	auto[0]	others[2]	1546	1			T10	4		T26	2		T29	1
auto[1]	auto[0]	others[3]	1692	1			T10	3		T26	2		T31	9
auto[1]	auto[0]	interest[1]	1015	1			T10	3		T31	2		T44	2
auto[1]	auto[0]	interest[4]	6047	1			T6	1		T10	12		T26	2
auto[1]	auto[0]	interest[64]	3008	1			T10	4		T26	5		T31	10

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal