Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2529018	1			T1	1		T2	1		T3	1
all_values[1]	2529018	1			T1	1		T2	1		T3	1
all_values[2]	2529018	1			T1	1		T2	1		T3	1
all_values[3]	2529018	1			T1	1		T2	1		T3	1
all_values[4]	2529018	1			T1	1		T2	1		T3	1
all_values[5]	2529018	1			T1	1		T2	1		T3	1
all_values[6]	2529018	1			T1	1		T2	1		T3	1
all_values[7]	2529018	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19324120

1

T1

8

T2

8

T3

8

auto[1]

908024

1

T37

82

T38

70

T39

97

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20205845

1

T1

8

T2

8

T3

8

auto[1]

26299

1

T47

1

T52

162

T53

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2348880	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	12014	1			T52	109		T53	2		T89	56
all_values[0]	auto[1]	auto[0]	167246	1			T37	5		T38	1		T39	5
all_values[0]	auto[1]	auto[1]	878	1			T37	2		T38	3		T39	4
all_values[1]	auto[0]	auto[0]	2469256	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	7806	1			T52	53		T89	37		T49	81
all_values[1]	auto[1]	auto[0]	51522	1			T37	8		T38	4		T39	10
all_values[1]	auto[1]	auto[1]	434	1			T37	3		T38	3		T39	2
all_values[2]	auto[0]	auto[0]	2473959	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	3088	1			T89	15		T93	35		T37	4
all_values[2]	auto[1]	auto[0]	51694	1			T37	7		T38	6		T39	8
all_values[2]	auto[1]	auto[1]	277	1			T37	5		T38	3		T39	7
all_values[3]	auto[0]	auto[0]	2373133	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	206	1			T47	1		T37	4		T38	1
all_values[3]	auto[1]	auto[0]	155517	1			T37	5		T38	7		T39	7
all_values[3]	auto[1]	auto[1]	162	1			T37	3		T38	3		T39	5
all_values[4]	auto[0]	auto[0]	2364133	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	199	1			T37	3		T38	2		T186	1
all_values[4]	auto[1]	auto[0]	164499	1			T37	12		T38	8		T39	9
all_values[4]	auto[1]	auto[1]	187	1			T37	5		T38	4		T40	7
all_values[5]	auto[0]	auto[0]	2417807	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	176	1			T37	5		T38	1		T39	1
all_values[5]	auto[1]	auto[0]	110868	1			T37	5		T38	7		T39	12
all_values[5]	auto[1]	auto[1]	167	1			T37	2		T38	4		T39	4
all_values[6]	auto[0]	auto[0]	2495745	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	160	1			T37	5		T38	2		T39	3
all_values[6]	auto[1]	auto[0]	32943	1			T37	3		T38	5		T39	5
all_values[6]	auto[1]	auto[1]	170	1			T37	6		T38	2		T39	3
all_values[7]	auto[0]	auto[0]	2357371	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	187	1			T37	4		T39	4		T40	3
all_values[7]	auto[1]	auto[0]	171272	1			T37	5		T38	8		T39	8
all_values[7]	auto[1]	auto[1]	188	1			T37	6		T38	2		T39	8