Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	37734	1			T9	6		T13	2		T14	12
auto[SpiFlashAddrCfg]	8208	1			T9	2		T14	4		T17	2
auto[SpiFlashAddr3b]	9555	1			T9	2		T13	6		T18	2
auto[SpiFlashAddr4b]	7989	1			T9	4		T13	4		T14	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36525

1

T9

14

T13

12

T14

18

auto[1]

26961

1

T17

4

T21

14

T57

4

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33895

1

T9

6

T13

8

T14

12

auto[1]

29591

1

T9

8

T13

4

T14

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	42399	1			T9	6		T13	8		T14	6
values[1]	1172	1			T14	4		T18	2		T52	5
values[2]	1523	1			T13	4		T19	2		T21	2
values[3]	1564	1			T72	2		T52	5		T91	8
values[4]	1517	1			T17	2		T62	6		T52	3
values[5]	1654	1			T14	2		T19	4		T55	4
values[6]	1735	1			T52	6		T79	2		T53	3
values[7]	1633	1			T47	2		T72	2		T74	3
values[8]	10289	1			T9	8		T14	6		T17	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33694

1

T9

14

T13

12

T14

18

auto[1]

29792

1

T47

2

T56

2

T74

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

60141

1

T9

10

T13

12

T14

18

write

3345

1

T9

4

T57

2

T52

9

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20338

1

T9

2

T14

10

T17

2

valids[0x1]

43148

1

T9

12

T13

12

T14

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1684	1			T59	2		T62	2		T52	7
internal_process_ops[0x5a]	1648	1			T13	6		T59	4		T62	4
internal_process_ops[0x05]	22950	1			T9	2		T59	2		T75	4
internal_process_ops[0x35]	1623	1			T14	2		T22	2		T52	6
internal_process_ops[0x15]	1677	1			T13	2		T22	4		T59	4
internal_process_ops[0x03]	1049	1			T17	2		T19	2		T59	2
internal_process_ops[0x0b]	1085	1			T13	4		T47	2		T56	2
internal_process_ops[0x3b]	1075	1			T14	2		T52	1		T79	2
internal_process_ops[0x6b]	1123	1			T19	2		T57	2		T59	4
internal_process_ops[0xbb]	1137	1			T19	4		T21	2		T55	4
internal_process_ops[0xeb]	1106	1			T14	4		T55	2		T74	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61827

1

T9

14

T13

12

T14

18

auto[1]

1659

1

T57

2

T52

7

T53

7

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61118

1

T9

14

T13

12

T14

18

auto[1]

2368

1

T52

10

T53

7

T54

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11674

1

T9

6

T13

2

T14

12

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7364

1

T60

2

T63

30

T65

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2209

1

T14

4

T22

2

T55

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1948

1

T17

2

T21

2

T57

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2586

1

T9

2

T13

6

T18

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2300

1

T21

10

T63

23

T65

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2149

1

T9

2

T13

4

T14

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1879

1

T17

2

T21

2

T63

28

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

100

1

T50

1

T51

2

T100

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

80

1

T63

1

T49

2

T50

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

76

1

T49

1

T68

1

T50

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

99

1

T63

1

T49

1

T69

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

126

1

T9

2

T68

2

T50

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

108

1

T176

1

T100

4

T39

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

97

1

T50

3

T142

1

T177

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

131

1

T63

2

T65

2

T49

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

98

1

T63

1

T49

2

T66

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

79

1

T63

2

T49

1

T50

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

89

1

T63

4

T50

4

T178

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

108

1

T57

2

T49

1

T50

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

99

1

T9

2

T58

2

T179

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

88

1

T67

1

T68

3

T50

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

90

1

T50

3

T176

1

T100

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

117

1

T63

2

T65

4

T49

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11100

1

T52

47

T53

181

T54

38

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6788

1

T52

36

T53

29

T54

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1552

1

T47

2

T56

2

T52

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1553

1

T52

10

T53

15

T54

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1916

1

T74

5

T52

10

T53

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1935

1

T52

23

T53

10

T54

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1641

1

T52

7

T53

8

T54

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1547

1

T52

12

T53

20

T54

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

114

1

T53

1

T54

1

T77

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

121

1

T52

6

T54

2

T88

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

109

1

T77

2

T98

3

T109

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

109

1

T88

1

T89

1

T98

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

132

1

T88

2

T98

1

T109

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

116

1

T53

4

T77

3

T89

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

120

1

T52

1

T98

1

T99

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

116

1

T77

3

T99

4

T180

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

117

1

T52

1

T54

1

T77

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

112

1

T89

2

T181

1

T99

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

126

1

T53

4

T109

1

T99

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

89

1

T53

1

T88

2

T89

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

111

1

T77

1

T98

1

T181

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

97

1

T88

1

T181

2

T93

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

82

1

T109

2

T181

5

T37

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

89

1

T52

1

T53

2

T109

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4022	1			T14	4		T20	10		T61	8
auto[0]	values[0]	valids[0x1]	17819	1			T9	6		T13	8		T14	2
auto[0]	values[1]	valids[0x1]	555	1			T14	4		T18	2		T63	4
auto[0]	values[2]	valids[0x0]	539	1			T21	2		T59	4		T63	8
auto[0]	values[2]	valids[0x1]	319	1			T13	4		T19	2		T59	4
auto[0]	values[3]	valids[0x0]	538	1			T72	2		T91	8		T182	2
auto[0]	values[3]	valids[0x1]	363	1			T49	8		T183	4		T68	2
auto[0]	values[4]	valids[0x0]	556	1			T17	2		T62	6		T58	2
auto[0]	values[4]	valids[0x1]	305	1			T58	2		T60	2		T63	2
auto[0]	values[5]	valids[0x0]	611	1			T19	4		T55	4		T62	4
auto[0]	values[5]	valids[0x1]	358	1			T14	2		T59	2		T63	3
auto[0]	values[6]	valids[0x0]	617	1			T79	2		T63	9		T49	2
auto[0]	values[6]	valids[0x1]	329	1			T63	1		T65	2		T184	2
auto[0]	values[7]	valids[0x0]	635	1			T72	2		T182	2		T63	13
auto[0]	values[7]	valids[0x1]	302	1			T185	4		T63	3		T49	1
auto[0]	values[8]	valids[0x0]	3667	1			T9	2		T14	6		T19	2
auto[0]	values[8]	valids[0x1]	2159	1			T9	6		T17	2		T21	10
auto[1]	values[0]	valids[0x0]	4138	1			T52	25		T53	33		T54	10
auto[1]	values[0]	valids[0x1]	16420	1			T56	2		T52	81		T53	184
auto[1]	values[1]	valids[0x1]	617	1			T52	5		T53	5		T54	2
auto[1]	values[2]	valids[0x0]	406	1			T52	3		T53	2		T54	2
auto[1]	values[2]	valids[0x1]	259	1			T52	1		T53	4		T89	4
auto[1]	values[3]	valids[0x0]	375	1			T52	2		T53	4		T77	1
auto[1]	values[3]	valids[0x1]	288	1			T52	3		T53	4		T54	2
auto[1]	values[4]	valids[0x0]	402	1			T52	2		T53	4		T54	1
auto[1]	values[4]	valids[0x1]	254	1			T52	1		T53	3		T54	2
auto[1]	values[5]	valids[0x0]	413	1			T53	2		T54	2		T77	1
auto[1]	values[5]	valids[0x1]	272	1			T52	1		T77	1		T88	1
auto[1]	values[6]	valids[0x0]	453	1			T52	2		T53	1		T77	4
auto[1]	values[6]	valids[0x1]	336	1			T52	4		T53	2		T77	1
auto[1]	values[7]	valids[0x0]	428	1			T52	2		T53	1		T54	1
auto[1]	values[7]	valids[0x1]	268	1			T47	2		T74	3		T77	4
auto[1]	values[8]	valids[0x0]	2538	1			T74	2		T52	18		T53	19
auto[1]	values[8]	valids[0x1]	1925	1			T52	8		T53	21		T54	4