Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3749319

1

T7

1

T9

1

T13

1513

auto[1]

27917

1

T52

38

T53

149

T54

28

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1203227

1

T7

1

T9

1

T13

1513

auto[1]

2574009

1

T14

1024

T59

604

T75

5514

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	712648	1			T7	1		T9	1		T13	183
auto[524288:1048575]	473275	1			T13	387		T55	1277		T59	194
auto[1048576:1572863]	361992	1			T13	105		T19	84		T55	198
auto[1572864:2097151]	457432	1			T13	123		T20	8		T47	14
auto[2097152:2621439]	392136	1			T13	244		T56	869		T59	986
auto[2621440:3145727]	433699	1			T13	116		T19	414		T55	6
auto[3145728:3670015]	475780	1			T19	163		T20	1		T55	309
auto[3670016:4194303]	470274	1			T13	355		T19	129		T56	2252

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2606877

1

T7

1

T9

1

T13

243

auto[1]

1170359

1

T13

1270

T19

1048

T47

380

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3317057

1

T7

1

T9

1

T13

1513

auto[1]

460179

1

T52

1339

T53

818

T54

2524

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	259443	1			T7	1		T9	1		T13	183
auto[0]	auto[0]	auto[0:524287]	auto[1]	400517	1			T14	1024		T59	39		T75	2745
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	157142	1			T13	387		T55	1277		T59	193
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	256428	1			T59	1		T52	131		T54	24
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	85548	1			T13	105		T19	84		T55	198
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	215769	1			T59	2		T52	2		T78	4390
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	119726	1			T13	123		T20	8		T47	14
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	266920	1			T75	2		T52	1		T53	257
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	112174	1			T13	244		T56	869		T59	676
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	204711	1			T59	310		T78	4		T79	569
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	152003	1			T13	116		T19	414		T55	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	224836	1			T59	252		T52	260		T78	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	137256	1			T19	163		T20	1		T55	309
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	278639	1			T75	2762		T52	1562		T53	384
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	162272	1			T13	355		T19	129		T56	2252
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	261155	1			T75	5		T78	3		T79	2
auto[0]	auto[1]	auto[0:524287]	auto[0]	3063	1			T270	1750		T63	1		T201	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	45057	1			T63	768		T89	794		T49	1384
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2552	1			T52	1		T53	2		T54	8
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	53667	1			T52	512		T53	269		T54	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	686	1			T52	1		T270	2		T77	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	56693	1			T54	2479		T63	256		T49	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	561	1			T53	3		T54	1		T63	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	67558	1			T53	1		T54	1		T63	2562
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1726	1			T52	2		T53	1		T54	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	70723	1			T52	809		T54	1		T77	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	601	1			T53	4		T88	1		T89	8
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	52506	1			T53	1		T63	256		T89	642
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2857	1			T54	1		T270	1813		T63	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	53534	1			T52	5		T54	1		T50	2929
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2106	1			T53	3		T63	6		T89	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	40890	1			T53	482		T63	2		T89	261
auto[1]	auto[0]	auto[0:524287]	auto[0]	428	1			T89	1		T49	5		T66	6
auto[1]	auto[0]	auto[0:524287]	auto[1]	3333	1			T89	1		T49	35		T66	182
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	371	1			T52	1		T63	1		T51	16
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2600	1			T52	1		T63	12		T51	124
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	371	1			T52	2		T63	2		T77	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1990	1			T52	5		T63	29		T49	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	322	1			T52	1		T53	1		T88	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1791	1			T52	1		T53	8		T88	10
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	274	1			T53	2		T63	1		T77	9
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1940	1			T53	31		T63	16		T77	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	383	1			T53	1		T77	3		T88	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2687	1			T53	15		T88	88		T67	23
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	365	1			T52	5		T77	4		T50	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2350	1			T52	13		T50	64		T176	24
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	348	1			T53	1		T63	1		T77	19
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2965	1			T53	38		T63	3		T77	20
auto[1]	auto[1]	auto[0:524287]	auto[0]	97	1			T89	1		T49	1		T50	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	710	1			T89	3		T49	29		T50	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	61	1			T54	1		T49	2		T98	8
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	454	1			T54	2		T49	3		T98	6
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	74	1			T70	1		T93	5		T100	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	861	1			T70	13		T93	21		T100	104
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	71	1			T53	1		T54	1		T49	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	483	1			T53	9		T54	11		T49	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	109	1			T52	1		T54	1		T77	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	479	1			T52	8		T54	5		T38	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	74	1			T53	1		T89	2		T49	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	609	1			T53	41		T49	3		T68	51
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	65	1			T54	1		T50	3		T176	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	714	1			T54	6		T50	53		T176	27
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	98	1			T63	2		T68	4		T70	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	440	1			T63	53		T70	72		T181	26

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2134667	1			T7	1		T9	1		T13	243
auto[0]	auto[0]	auto[1]	1159872	1			T13	1270		T19	1048		T47	380
auto[0]	auto[1]	auto[0]	444926	1			T52	1330		T53	765		T54	2493
auto[0]	auto[1]	auto[1]	9854	1			T53	1		T54	3		T270	5335
auto[1]	auto[0]	auto[0]	22000	1			T52	28		T53	94		T63	63
auto[1]	auto[0]	auto[1]	518	1			T52	1		T53	3		T63	2
auto[1]	auto[1]	auto[0]	5284	1			T52	9		T53	51		T54	26
auto[1]	auto[1]	auto[1]	115	1			T53	1		T54	2		T63	1