Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2529018	1			T1	1		T2	1		T3	1
all_pins[1]	2529018	1			T1	1		T2	1		T3	1
all_pins[2]	2529018	1			T1	1		T2	1		T3	1
all_pins[3]	2529018	1			T1	1		T2	1		T3	1
all_pins[4]	2529018	1			T1	1		T2	1		T3	1
all_pins[5]	2529018	1			T1	1		T2	1		T3	1
all_pins[6]	2529018	1			T1	1		T2	1		T3	1
all_pins[7]	2529018	1			T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20195315	1			T1	8		T2	8		T3	8
values[0x1]	36829	1			T37	32		T38	24		T39	33
transitions[0x0=>0x1]	35518	1			T37	21		T38	13		T39	24
transitions[0x1=>0x0]	35532	1			T37	21		T38	13		T39	24

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2528067	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	951	1			T37	2		T38	3		T39	4
all_pins[0]	transitions[0x0=>0x1]	622	1			T37	2		T38	3		T39	4
all_pins[0]	transitions[0x1=>0x0]	137	1			T37	3		T38	3		T39	2
all_pins[1]	values[0x0]	2528552	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	466	1			T37	3		T38	3		T39	2
all_pins[1]	transitions[0x0=>0x1]	316	1			T37	3		T38	1		T39	1
all_pins[1]	transitions[0x1=>0x0]	138	1			T37	5		T38	1		T39	6
all_pins[2]	values[0x0]	2528730	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	288	1			T37	5		T38	3		T39	7
all_pins[2]	transitions[0x0=>0x1]	237	1			T37	4		T38	1		T39	3
all_pins[2]	transitions[0x1=>0x0]	111	1			T37	2		T38	1		T39	1
all_pins[3]	values[0x0]	2528856	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	162	1			T37	3		T38	3		T39	5
all_pins[3]	transitions[0x0=>0x1]	112	1			T37	1		T39	5		T150	2
all_pins[3]	transitions[0x1=>0x0]	137	1			T37	3		T38	1		T40	7
all_pins[4]	values[0x0]	2528831	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	187	1			T37	5		T38	4		T40	7
all_pins[4]	transitions[0x0=>0x1]	150	1			T37	4		T38	3		T40	6
all_pins[4]	transitions[0x1=>0x0]	1819	1			T37	1		T38	3		T39	4
all_pins[5]	values[0x0]	2527162	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	1856	1			T37	2		T38	4		T39	4
all_pins[5]	transitions[0x0=>0x1]	1253	1			T38	3		T39	3		T40	3
all_pins[5]	transitions[0x1=>0x0]	32128	1			T37	4		T38	1		T39	2
all_pins[6]	values[0x0]	2496287	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	32731	1			T37	6		T38	2		T39	3
all_pins[6]	transitions[0x0=>0x1]	32693	1			T37	2		T38	1		T39	2
all_pins[6]	transitions[0x1=>0x0]	150	1			T37	2		T38	1		T39	7
all_pins[7]	values[0x0]	2528830	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	188	1			T37	6		T38	2		T39	8
all_pins[7]	transitions[0x0=>0x1]	135	1			T37	5		T38	1		T39	6
all_pins[7]	transitions[0x1=>0x0]	912	1			T37	1		T38	2		T39	2