Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19396

1

T9

14

T13

12

T14

18

auto[1]

14298

1

T17

4

T21

14

T57

4

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3925	1			T9	14		T13	12		T75	6
values[1]	4318	1			T17	4		T72	6		T63	68
values[2]	3813	1			T22	10		T63	40		T49	29
values[3]	4299	1			T19	8		T58	10		T49	38
values[4]	4150	1			T57	4		T90	4		T270	4
values[5]	4690	1			T61	8		T185	4		T60	6
values[6]	4612	1			T18	2		T20	10		T21	14
values[7]	3887	1			T14	18		T55	6		T59	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4394	1			T22	10		T59	20		T270	4
values[1]	4195	1			T14	18		T91	10		T58	10
values[2]	4668	1			T9	14		T21	14		T72	6
values[3]	4007	1			T13	12		T75	6		T271	2
values[4]	4059	1			T18	2		T61	8		T63	129
values[5]	3720	1			T57	4		T78	18		T79	6
values[6]	4518	1			T19	8		T20	10		T55	6
values[7]	4133	1			T17	4		T90	4		T49	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	196	1			T51	14		T272	20		T273	11
auto[0]	values[0]	values[1]	444	1			T100	71		T150	12		T274	12
auto[0]	values[0]	values[2]	250	1			T9	14		T63	26		T67	13
auto[0]	values[0]	values[3]	388	1			T13	12		T75	6		T201	6
auto[0]	values[0]	values[4]	256	1			T63	11		T100	8		T177	15
auto[0]	values[0]	values[5]	181	1			T253	12		T275	2		T178	22
auto[0]	values[0]	values[6]	305	1			T276	6		T277	14		T278	11
auto[0]	values[0]	values[7]	324	1			T279	6		T39	12		T150	8
auto[0]	values[1]	values[0]	420	1			T142	16		T264	5		T108	9
auto[0]	values[1]	values[1]	381	1			T67	11		T50	14		T267	10
auto[0]	values[1]	values[2]	284	1			T72	6		T49	24		T176	67
auto[0]	values[1]	values[3]	226	1			T240	18		T280	56		T281	11
auto[0]	values[1]	values[4]	248	1			T282	6		T283	10		T204	12
auto[0]	values[1]	values[5]	400	1			T63	57		T184	6		T118	2
auto[0]	values[1]	values[6]	209	1			T64	14		T263	2		T203	12
auto[0]	values[1]	values[7]	409	1			T227	10		T100	12		T225	12
auto[0]	values[2]	values[0]	164	1			T22	10		T50	15		T284	6
auto[0]	values[2]	values[1]	147	1			T68	13		T177	12		T108	11
auto[0]	values[2]	values[2]	327	1			T50	45		T100	13		T253	15
auto[0]	values[2]	values[3]	241	1			T256	10		T39	9		T212	15
auto[0]	values[2]	values[4]	367	1			T63	8		T100	102		T200	11
auto[0]	values[2]	values[5]	318	1			T63	13		T212	14		T285	14
auto[0]	values[2]	values[6]	366	1			T49	17		T51	9		T246	18
auto[0]	values[2]	values[7]	246	1			T286	2		T208	12		T264	42
auto[0]	values[3]	values[0]	319	1			T50	15		T100	53		T177	16
auto[0]	values[3]	values[1]	357	1			T58	10		T241	20		T249	9
auto[0]	values[3]	values[2]	362	1			T50	13		T70	8		T51	15
auto[0]	values[3]	values[3]	355	1			T253	13		T264	29		T287	4
auto[0]	values[3]	values[4]	307	1			T49	12		T150	16		T236	10
auto[0]	values[3]	values[5]	271	1			T288	47		T174	8		T289	8
auto[0]	values[3]	values[6]	405	1			T19	8		T51	14		T100	158
auto[0]	values[3]	values[7]	171	1			T100	11		T290	4		T150	11
auto[0]	values[4]	values[0]	285	1			T270	4		T49	26		T179	18
auto[0]	values[4]	values[1]	188	1			T177	11		T253	11		T247	8
auto[0]	values[4]	values[2]	360	1			T63	7		T68	10		T51	10
auto[0]	values[4]	values[3]	494	1			T271	2		T68	10		T51	13
auto[0]	values[4]	values[4]	280	1			T51	8		T291	2		T264	8
auto[0]	values[4]	values[5]	321	1			T50	15		T150	15		T236	11
auto[0]	values[4]	values[6]	274	1			T94	4		T217	18		T253	14
auto[0]	values[4]	values[7]	226	1			T90	4		T49	11		T292	6
auto[0]	values[5]	values[0]	321	1			T144	8		T100	14		T266	55
auto[0]	values[5]	values[1]	358	1			T202	12		T253	17		T175	10
auto[0]	values[5]	values[2]	303	1			T185	4		T50	51		T51	10
auto[0]	values[5]	values[3]	165	1			T215	18		T293	6		T294	4
auto[0]	values[5]	values[4]	192	1			T61	8		T295	12		T51	11
auto[0]	values[5]	values[5]	261	1			T51	15		T39	12		T224	10
auto[0]	values[5]	values[6]	398	1			T296	6		T207	12		T232	17
auto[0]	values[5]	values[7]	270	1			T50	10		T176	21		T207	14
auto[0]	values[6]	values[0]	158	1			T50	11		T218	12		T273	14
auto[0]	values[6]	values[1]	328	1			T63	33		T49	13		T297	6
auto[0]	values[6]	values[2]	311	1			T150	11		T274	9		T212	10
auto[0]	values[6]	values[3]	319	1			T298	2		T299	8		T240	11
auto[0]	values[6]	values[4]	432	1			T18	2		T63	71		T51	11
auto[0]	values[6]	values[5]	233	1			T78	18		T49	10		T39	11
auto[0]	values[6]	values[6]	344	1			T20	10		T62	16		T51	11
auto[0]	values[6]	values[7]	377	1			T223	20		T264	9		T150	14
auto[0]	values[7]	values[0]	245	1			T59	20		T51	17		T218	8
auto[0]	values[7]	values[1]	334	1			T14	18		T91	10		T49	17
auto[0]	values[7]	values[2]	202	1			T68	11		T221	8		T277	23
auto[0]	values[7]	values[3]	315	1			T100	12		T300	10		T249	10
auto[0]	values[7]	values[4]	271	1			T68	16		T255	16		T301	22
auto[0]	values[7]	values[5]	208	1			T79	6		T63	13		T49	21
auto[0]	values[7]	values[6]	436	1			T55	6		T182	4		T49	69
auto[0]	values[7]	values[7]	543	1			T66	206		T67	12		T50	17
auto[1]	values[0]	values[0]	148	1			T51	6		T273	9		T277	41
auto[1]	values[0]	values[1]	122	1			T100	12		T150	10		T274	10
auto[1]	values[0]	values[2]	144	1			T63	7		T67	7		T68	9
auto[1]	values[0]	values[3]	258	1			T50	24		T70	113		T100	6
auto[1]	values[0]	values[4]	251	1			T63	9		T100	25		T177	5
auto[1]	values[0]	values[5]	175	1			T253	8		T178	8		T247	13
auto[1]	values[0]	values[6]	266	1			T302	4		T277	57		T278	9
auto[1]	values[0]	values[7]	217	1			T39	10		T150	12		T240	8
auto[1]	values[1]	values[0]	313	1			T142	4		T264	43		T108	12
auto[1]	values[1]	values[1]	255	1			T67	75		T50	22		T178	9
auto[1]	values[1]	values[2]	265	1			T49	20		T176	7		T204	8
auto[1]	values[1]	values[3]	140	1			T240	2		T280	16		T281	14
auto[1]	values[1]	values[4]	295	1			T204	8		T232	57		T277	126
auto[1]	values[1]	values[5]	172	1			T63	11		T253	9		T303	2
auto[1]	values[1]	values[6]	125	1			T273	11		T232	11		T277	11
auto[1]	values[1]	values[7]	176	1			T17	4		T100	28		T304	24
auto[1]	values[2]	values[0]	165	1			T69	22		T50	5		T150	8
auto[1]	values[2]	values[1]	164	1			T68	7		T71	14		T177	8
auto[1]	values[2]	values[2]	455	1			T50	41		T100	70		T253	11
auto[1]	values[2]	values[3]	193	1			T239	14		T39	12		T212	6
auto[1]	values[2]	values[4]	204	1			T63	12		T100	5		T200	9
auto[1]	values[2]	values[5]	104	1			T63	7		T212	6		T178	4
auto[1]	values[2]	values[6]	206	1			T49	12		T51	11		T108	12
auto[1]	values[2]	values[7]	146	1			T264	7		T232	12		T169	55
auto[1]	values[3]	values[0]	344	1			T50	60		T100	8		T177	4
auto[1]	values[3]	values[1]	187	1			T249	11		T175	29		T240	7
auto[1]	values[3]	values[2]	366	1			T50	7		T70	160		T51	5
auto[1]	values[3]	values[3]	140	1			T253	10		T264	15		T231	6
auto[1]	values[3]	values[4]	205	1			T49	26		T150	8		T236	10
auto[1]	values[3]	values[5]	139	1			T174	12		T206	8		T108	22
auto[1]	values[3]	values[6]	212	1			T210	26		T51	6		T100	11
auto[1]	values[3]	values[7]	159	1			T183	18		T100	9		T305	22
auto[1]	values[4]	values[0]	196	1			T65	14		T49	12		T50	7
auto[1]	values[4]	values[1]	247	1			T177	9		T253	22		T306	16
auto[1]	values[4]	values[2]	254	1			T63	13		T68	10		T51	10
auto[1]	values[4]	values[3]	209	1			T68	10		T51	7		T212	12
auto[1]	values[4]	values[4]	179	1			T51	12		T264	13		T212	15
auto[1]	values[4]	values[5]	137	1			T57	4		T50	8		T150	5
auto[1]	values[4]	values[6]	254	1			T253	6		T175	67		T204	8
auto[1]	values[4]	values[7]	246	1			T49	9		T177	82		T307	7
auto[1]	values[5]	values[0]	893	1			T100	54		T308	67		T216	171
auto[1]	values[5]	values[1]	192	1			T202	15		T253	8		T175	63
auto[1]	values[5]	values[2]	233	1			T50	7		T51	10		T204	5
auto[1]	values[5]	values[3]	111	1			T294	19		T213	4		T309	11
auto[1]	values[5]	values[4]	224	1			T51	9		T204	8		T218	7
auto[1]	values[5]	values[5]	277	1			T60	6		T51	5		T39	8
auto[1]	values[5]	values[6]	231	1			T207	34		T232	7		T200	14
auto[1]	values[5]	values[7]	261	1			T50	42		T176	8		T207	6
auto[1]	values[6]	values[0]	98	1			T50	23		T218	8		T273	9
auto[1]	values[6]	values[1]	265	1			T63	17		T49	7		T310	2
auto[1]	values[6]	values[2]	331	1			T21	14		T150	9		T274	11
auto[1]	values[6]	values[3]	264	1			T240	15		T178	7		T168	12
auto[1]	values[6]	values[4]	221	1			T63	18		T51	9		T100	11
auto[1]	values[6]	values[5]	411	1			T49	10		T39	12		T150	9
auto[1]	values[6]	values[6]	312	1			T51	9		T254	12		T311	18
auto[1]	values[6]	values[7]	208	1			T264	11		T150	6		T108	15
auto[1]	values[7]	values[0]	129	1			T51	3		T218	13		T312	7
auto[1]	values[7]	values[1]	226	1			T49	8		T176	22		T212	6
auto[1]	values[7]	values[2]	221	1			T68	9		T313	22		T277	63
auto[1]	values[7]	values[3]	189	1			T100	49		T249	35		T314	6
auto[1]	values[7]	values[4]	127	1			T68	4		T212	13		T315	23
auto[1]	values[7]	values[5]	112	1			T63	7		T49	9		T39	5
auto[1]	values[7]	values[6]	175	1			T49	9		T39	10		T108	8
auto[1]	values[7]	values[7]	154	1			T67	8		T50	3		T204	8