Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	396	1			T19	6		T55	2		T59	8
auto[ReadAddrCrossIntoMailbox]	338	1			T55	2		T185	2		T49	1
auto[ReadAddrCrossOutOfMailbox]	326	1			T63	1		T49	1		T67	2
auto[ReadAddrCrossAllMailbox]	237	1			T55	2		T185	2		T67	1
auto[ReadAddrOutsideMailbox]	3647	1			T13	4		T14	6		T17	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2399

1

T13

2

T14

3

T17

1

auto[1]

2545

1

T13

2

T14

3

T17

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	777	1			T17	2		T19	2		T59	2
read_ops[0x0b]	814	1			T13	4		T79	2		T185	4
read_ops[0x3b]	822	1			T14	2		T79	2		T63	3
read_ops[0x6b]	843	1			T19	2		T57	2		T59	4
read_ops[0xbb]	881	1			T19	4		T21	2		T55	4
read_ops[0xeb]	807	1			T14	4		T55	2		T91	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	45	1			T19	1		T59	1		T67	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T19	1		T59	1		T68	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T142	1		T150	2		T175	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T68	1		T70	1		T176	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T51	1		T39	1		T249	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T49	1		T70	1		T264	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T175	1		T236	1		T207	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T100	1		T274	1		T247	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	257	1			T17	1		T63	1		T94	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	282	1			T17	1		T63	3		T94	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T68	1		T215	1		T264	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T215	1		T100	1		T175	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T185	1		T100	1		T249	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T185	1		T150	2		T175	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T150	3		T212	2		T247	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T67	1		T50	1		T212	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T185	1		T67	1		T174	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T185	1		T264	1		T108	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	301	1			T13	2		T79	1		T63	6
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	320	1			T13	2		T79	1		T63	6
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T51	1		T100	1		T212	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T264	1		T212	1		T175	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T150	1		T175	2		T247	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T68	1		T100	1		T175	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T68	1		T176	1		T100	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T68	1		T142	1		T100	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T68	1		T100	2		T212	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T142	1		T249	1		T169	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T14	1		T79	1		T63	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	330	1			T14	1		T79	1		T63	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T59	2		T49	1		T50	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T59	2		T63	1		T68	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T49	1		T142	1		T175	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T68	2		T50	2		T206	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T39	1		T264	1		T150	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T63	1		T100	1		T264	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	30	1			T202	1		T253	1		T264	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T176	1		T249	1		T108	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	304	1			T19	1		T57	1		T91	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T19	1		T57	1		T91	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T19	2		T55	1		T59	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T19	2		T55	1		T59	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T55	1		T50	1		T70	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T55	1		T67	1		T68	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T100	1		T39	1		T283	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T67	1		T50	1		T174	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T264	1		T300	2		T150	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T39	2		T300	2		T249	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	309	1			T21	1		T72	1		T62	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	334	1			T21	1		T72	1		T62	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T300	1		T249	1		T240	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T51	1		T264	1		T300	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T50	1		T51	1		T100	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T68	1		T50	1		T100	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T178	1		T167	1		T168	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T39	1		T264	1		T249	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T55	1		T212	1		T308	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T55	1		T315	1		T108	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T14	2		T91	1		T182	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	326	1			T14	2		T91	1		T182	1