Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4968	1			T91	10		T63	69		T94	4
values[1]	4779	1			T9	14		T20	10		T78	18
values[2]	3939	1			T14	18		T17	4		T59	20
values[3]	3861	1			T18	2		T21	14		T49	78
values[4]	3734	1			T55	6		T57	4		T79	6
values[5]	4236	1			T13	12		T90	4		T65	14
values[6]	4307	1			T22	10		T72	6		T58	10
values[7]	3870	1			T19	8		T62	16		T201	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4197	1			T59	20		T91	10		T63	89
values[1]	3727	1			T21	14		T75	6		T63	20
values[2]	4706	1			T61	8		T62	16		T63	20
values[3]	4409	1			T13	12		T55	6		T57	4
values[4]	4171	1			T79	6		T63	20		T49	38
values[5]	4017	1			T9	14		T17	4		T18	2
values[6]	4627	1			T72	6		T185	4		T63	101
values[7]	3840	1			T14	18		T19	8		T20	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32884

1

T9

14

T13

12

T14

18

auto[1]

810

1

T57

2

T63

8

T65

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	661	1			T91	10		T63	69		T94	4
auto[0]	values[0]	values[1]	621	1			T50	20		T249	20		T242	24
auto[0]	values[0]	values[2]	754	1			T49	24		T253	31		T150	19
auto[0]	values[0]	values[3]	580	1			T150	20		T175	20		T178	20
auto[0]	values[0]	values[4]	526	1			T51	16		T39	32		T175	59
auto[0]	values[0]	values[5]	653	1			T50	32		T282	6		T100	61
auto[0]	values[0]	values[6]	477	1			T66	206		T51	20		T100	40
auto[0]	values[0]	values[7]	579	1			T178	39		T247	20		T308	57
auto[0]	values[1]	values[0]	590	1			T255	16		T299	8		T317	10
auto[0]	values[1]	values[1]	461	1			T208	12		T264	20		T175	49
auto[0]	values[1]	values[2]	431	1			T49	20		T279	6		T264	24
auto[0]	values[1]	values[3]	569	1			T63	40		T68	35		T108	30
auto[0]	values[1]	values[4]	593	1			T253	46		T249	20		T285	14
auto[0]	values[1]	values[5]	729	1			T9	14		T64	14		T69	20
auto[0]	values[1]	values[6]	956	1			T150	20		T283	10		T236	25
auto[0]	values[1]	values[7]	342	1			T20	10		T78	18		T231	25
auto[0]	values[2]	values[0]	393	1			T59	20		T263	2		T276	6
auto[0]	values[2]	values[1]	488	1			T75	6		T63	19		T51	20
auto[0]	values[2]	values[2]	680	1			T61	8		T67	86		T50	20
auto[0]	values[2]	values[3]	548	1			T50	54		T232	70		T169	19
auto[0]	values[2]	values[4]	444	1			T51	19		T100	61		T318	20
auto[0]	values[2]	values[5]	415	1			T17	4		T63	48		T288	47
auto[0]	values[2]	values[6]	503	1			T63	68		T50	20		T222	20
auto[0]	values[2]	values[7]	395	1			T14	18		T253	20		T150	20
auto[0]	values[3]	values[0]	465	1			T49	78		T70	165		T51	20
auto[0]	values[3]	values[1]	647	1			T21	14		T217	18		T68	20
auto[0]	values[3]	values[2]	336	1			T67	19		T175	33		T306	10
auto[0]	values[3]	values[3]	534	1			T50	46		T100	142		T39	22
auto[0]	values[3]	values[4]	443	1			T275	2		T178	20		T273	21
auto[0]	values[3]	values[5]	465	1			T18	2		T177	92		T264	21
auto[0]	values[3]	values[6]	297	1			T319	22		T39	22		T175	20
auto[0]	values[3]	values[7]	571	1			T183	18		T178	20		T232	39
auto[0]	values[4]	values[0]	472	1			T63	18		T286	2		T176	27
auto[0]	values[4]	values[1]	446	1			T50	74		T203	12		T51	19
auto[0]	values[4]	values[2]	519	1			T253	23		T300	10		T206	19
auto[0]	values[4]	values[3]	391	1			T55	6		T57	2		T215	18
auto[0]	values[4]	values[4]	395	1			T79	6		T50	52		T227	10
auto[0]	values[4]	values[5]	473	1			T264	46		T150	24		T108	16
auto[0]	values[4]	values[6]	463	1			T150	22		T108	20		T238	22
auto[0]	values[4]	values[7]	468	1			T184	6		T295	12		T144	8
auto[0]	values[5]	values[0]	369	1			T271	2		T49	50		T212	19
auto[0]	values[5]	values[1]	361	1			T176	20		T249	43		T221	8
auto[0]	values[5]	values[2]	610	1			T231	20		T220	14		T308	20
auto[0]	values[5]	values[3]	776	1			T13	12		T68	20		T50	58
auto[0]	values[5]	values[4]	542	1			T68	19		T267	10		T200	19
auto[0]	values[5]	values[5]	499	1			T202	26		T51	18		T100	169
auto[0]	values[5]	values[6]	376	1			T65	8		T51	19		T308	20
auto[0]	values[5]	values[7]	601	1			T90	4		T67	20		T50	20
auto[0]	values[6]	values[0]	614	1			T70	124		T241	20		T254	10
auto[0]	values[6]	values[1]	391	1			T49	19		T179	18		T239	12
auto[0]	values[6]	values[2]	603	1			T63	20		T49	20		T223	20
auto[0]	values[6]	values[3]	368	1			T320	12		T268	2		T100	82
auto[0]	values[6]	values[4]	603	1			T63	19		T49	38		T240	50
auto[0]	values[6]	values[5]	324	1			T58	10		T60	6		T49	38
auto[0]	values[6]	values[6]	950	1			T72	6		T185	4		T63	31
auto[0]	values[6]	values[7]	354	1			T22	10		T270	4		T182	4
auto[0]	values[7]	values[0]	532	1			T118	2		T68	18		T71	12
auto[0]	values[7]	values[1]	217	1			T212	19		T321	6		T322	6
auto[0]	values[7]	values[2]	658	1			T62	16		T49	27		T50	20
auto[0]	values[7]	values[3]	540	1			T100	33		T177	38		T264	49
auto[0]	values[7]	values[4]	512	1			T298	2		T316	14		T212	20
auto[0]	values[7]	values[5]	355	1			T201	6		T49	20		T176	17
auto[0]	values[7]	values[6]	518	1			T175	18		T240	20		T323	2
auto[0]	values[7]	values[7]	438	1			T19	8		T50	57		T211	6
auto[1]	values[0]	values[0]	10	1			T200	1		T171	2		T172	2
auto[1]	values[0]	values[1]	18	1			T324	1		T214	2		T325	2
auto[1]	values[0]	values[2]	29	1			T49	1		T253	2		T150	1
auto[1]	values[0]	values[3]	15	1			T232	2		T200	2		T308	2
auto[1]	values[0]	values[4]	18	1			T51	4		T39	1		T175	3
auto[1]	values[0]	values[5]	18	1			T50	2		T100	2		T150	2
auto[1]	values[0]	values[6]	2	1			T280	1		T326	1		-	-
auto[1]	values[0]	values[7]	7	1			T178	1		T308	2		T230	1
auto[1]	values[1]	values[0]	17	1			T277	1		T172	2		T327	4
auto[1]	values[1]	values[1]	13	1			T175	1		T204	2		T303	2
auto[1]	values[1]	values[2]	2	1			T328	2		-	-		-	-
auto[1]	values[1]	values[3]	16	1			T68	5		T108	2		T200	2
auto[1]	values[1]	values[4]	14	1			T253	2		T168	3		T304	2
auto[1]	values[1]	values[5]	14	1			T69	2		T100	1		T207	3
auto[1]	values[1]	values[6]	16	1			T207	1		T169	4		T205	1
auto[1]	values[1]	values[7]	16	1			T231	4		T307	1		T281	1
auto[1]	values[2]	values[0]	6	1			T329	2		T330	4		-	-
auto[1]	values[2]	values[1]	5	1			T63	1		T176	2		T236	1
auto[1]	values[2]	values[2]	12	1			T174	1		T240	2		T277	1
auto[1]	values[2]	values[3]	15	1			T232	2		T169	1		T200	2
auto[1]	values[2]	values[4]	9	1			T51	1		T294	1		T331	2
auto[1]	values[2]	values[5]	14	1			T63	2		T294	2		T332	4
auto[1]	values[2]	values[6]	4	1			T216	1		T333	2		T330	1
auto[1]	values[2]	values[7]	8	1			T281	1		T334	1		T335	2
auto[1]	values[3]	values[0]	9	1			T70	3		T336	4		T337	2
auto[1]	values[3]	values[1]	16	1			T236	1		T222	2		T338	1
auto[1]	values[3]	values[2]	16	1			T67	1		T175	2		T306	6
auto[1]	values[3]	values[3]	11	1			T310	2		T100	2		T218	1
auto[1]	values[3]	values[4]	6	1			T214	1		T339	1		T340	2
auto[1]	values[3]	values[5]	15	1			T177	2		T315	2		T200	3
auto[1]	values[3]	values[6]	11	1			T39	1		T108	2		T307	3
auto[1]	values[3]	values[7]	19	1			T232	4		T277	4		T216	3
auto[1]	values[4]	values[0]	8	1			T63	2		T176	2		T108	1
auto[1]	values[4]	values[1]	16	1			T50	1		T51	1		T273	1
auto[1]	values[4]	values[2]	18	1			T206	1		T178	3		T247	1
auto[1]	values[4]	values[3]	10	1			T57	2		T100	1		T39	1
auto[1]	values[4]	values[4]	19	1			T100	2		T172	4		T341	5
auto[1]	values[4]	values[5]	14	1			T264	2		T108	4		T172	1
auto[1]	values[4]	values[6]	11	1			T204	3		T329	2		T328	1
auto[1]	values[4]	values[7]	11	1			T150	1		T171	2		T342	2
auto[1]	values[5]	values[0]	13	1			T49	3		T212	2		T240	4
auto[1]	values[5]	values[1]	11	1			T249	2		T331	1		T343	2
auto[1]	values[5]	values[2]	7	1			T214	1		T326	4		T344	2
auto[1]	values[5]	values[3]	21	1			T50	1		T142	1		T212	3
auto[1]	values[5]	values[4]	13	1			T68	1		T200	1		T213	2
auto[1]	values[5]	values[5]	11	1			T202	1		T51	2		T345	3
auto[1]	values[5]	values[6]	11	1			T65	6		T51	1		T278	1
auto[1]	values[5]	values[7]	15	1			T39	1		T204	4		T207	2
auto[1]	values[6]	values[0]	15	1			T70	2		T254	2		T177	2
auto[1]	values[6]	values[1]	11	1			T49	1		T239	2		T264	2
auto[1]	values[6]	values[2]	12	1			T100	2		T39	2		T346	2
auto[1]	values[6]	values[3]	7	1			T100	1		T253	3		T108	1
auto[1]	values[6]	values[4]	22	1			T63	1		T240	3		T167	4
auto[1]	values[6]	values[5]	6	1			T100	1		T214	3		T347	1
auto[1]	values[6]	values[6]	20	1			T63	2		T177	1		T212	2
auto[1]	values[6]	values[7]	7	1			T331	2		T348	4		T349	1
auto[1]	values[7]	values[0]	23	1			T68	2		T71	2		T150	1
auto[1]	values[7]	values[1]	5	1			T212	1		T207	1		T347	3
auto[1]	values[7]	values[2]	19	1			T49	3		T177	1		T308	7
auto[1]	values[7]	values[3]	8	1			T273	1		T280	3		T213	2
auto[1]	values[7]	values[4]	12	1			T175	2		T277	4		T345	1
auto[1]	values[7]	values[5]	12	1			T176	3		T177	1		T231	2
auto[1]	values[7]	values[6]	12	1			T175	4		T278	1		T44	1
auto[1]	values[7]	values[7]	9	1			T50	1		T150	1		T240	2