Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	805	1			T37	18		T38	11		T39	17
all_values[1]	805	1			T37	18		T38	11		T39	17
all_values[2]	805	1			T37	18		T38	11		T39	17
all_values[3]	805	1			T37	18		T38	11		T39	17
all_values[4]	805	1			T37	18		T38	11		T39	17
all_values[5]	805	1			T37	18		T38	11		T39	17
all_values[6]	805	1			T37	18		T38	11		T39	17
all_values[7]	805	1			T37	18		T38	11		T39	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3409

1

T37

84

T38

46

T39

61

auto[1]

3031

1

T37

60

T38

42

T39

75

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2633

1

T37

68

T38

31

T39

63

auto[1]

3807

1

T37

76

T38

57

T39

73

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3738

1

T37

87

T38

46

T39

87

auto[1]

2702

1

T37

57

T38

42

T39

49

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	175	1			T37	7		T39	3		T40	3
all_values[0]	auto[0]	auto[0]	auto[1]	78	1			T37	1		T38	3		T39	1
all_values[0]	auto[0]	auto[1]	auto[0]	132	1			T37	2		T39	4		T40	3
all_values[0]	auto[0]	auto[1]	auto[1]	78	1			T37	1		T38	1		T39	2
all_values[0]	auto[1]	auto[0]	auto[1]	201	1			T37	7		T38	6		T39	5
all_values[0]	auto[1]	auto[1]	auto[1]	141	1			T38	1		T39	2		T40	1
all_values[1]	auto[0]	auto[0]	auto[0]	174	1			T37	8		T38	1		T39	3
all_values[1]	auto[0]	auto[0]	auto[1]	81	1			T38	1		T39	2		T40	1
all_values[1]	auto[0]	auto[1]	auto[0]	142	1			T37	3		T38	1		T39	6
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T37	1		T38	1		T40	2
all_values[1]	auto[1]	auto[0]	auto[1]	169	1			T37	3		T38	4		T39	4
all_values[1]	auto[1]	auto[1]	auto[1]	154	1			T37	3		T38	3		T39	2
all_values[2]	auto[0]	auto[0]	auto[0]	142	1			T37	3		T38	1		T39	5
all_values[2]	auto[0]	auto[0]	auto[1]	90	1			T37	2		T38	2		T40	1
all_values[2]	auto[0]	auto[1]	auto[0]	152	1			T37	4		T38	1		T39	2
all_values[2]	auto[0]	auto[1]	auto[1]	78	1			T37	1		T38	1		T39	4
all_values[2]	auto[1]	auto[0]	auto[1]	182	1			T37	4		T38	6		T39	4
all_values[2]	auto[1]	auto[1]	auto[1]	161	1			T37	4		T39	2		T40	1
all_values[3]	auto[0]	auto[0]	auto[0]	161	1			T37	8		T38	2		T39	4
all_values[3]	auto[0]	auto[0]	auto[1]	87	1			T37	2		T39	2		T40	2
all_values[3]	auto[0]	auto[1]	auto[0]	144	1			T37	1		T38	2		T39	1
all_values[3]	auto[0]	auto[1]	auto[1]	68	1			T37	1		T38	2		T39	5
all_values[3]	auto[1]	auto[0]	auto[1]	193	1			T37	4		T38	4		T39	4
all_values[3]	auto[1]	auto[1]	auto[1]	152	1			T37	2		T38	1		T39	1
all_values[4]	auto[0]	auto[0]	auto[0]	165	1			T37	1		T38	1		T39	4
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T38	1		T40	1		T150	1
all_values[4]	auto[0]	auto[1]	auto[0]	136	1			T37	8		T38	3		T39	7
all_values[4]	auto[0]	auto[1]	auto[1]	84	1			T37	2		T38	1		T39	1
all_values[4]	auto[1]	auto[0]	auto[1]	189	1			T37	4		T38	3		T39	4
all_values[4]	auto[1]	auto[1]	auto[1]	147	1			T37	3		T38	2		T39	1
all_values[5]	auto[0]	auto[0]	auto[0]	223	1			T37	7		T38	1		T39	4
all_values[5]	auto[0]	auto[1]	auto[0]	239	1			T37	4		T38	5		T39	8
all_values[5]	auto[1]	auto[0]	auto[1]	180	1			T37	6		T38	2		T39	2
all_values[5]	auto[1]	auto[1]	auto[1]	163	1			T37	1		T38	3		T39	3
all_values[6]	auto[0]	auto[0]	auto[0]	173	1			T37	5		T38	2		T39	4
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T37	1		T38	1		T39	1
all_values[6]	auto[0]	auto[1]	auto[0]	171	1			T37	2		T38	3		T39	5
all_values[6]	auto[0]	auto[1]	auto[1]	71	1			T37	3		T38	1		T175	2
all_values[6]	auto[1]	auto[0]	auto[1]	154	1			T37	3		T38	2		T39	1
all_values[6]	auto[1]	auto[1]	auto[1]	166	1			T37	4		T38	2		T39	6
all_values[7]	auto[0]	auto[0]	auto[0]	165	1			T37	3		T38	3		T39	1
all_values[7]	auto[0]	auto[0]	auto[1]	82	1			T37	1		T39	1		T40	4
all_values[7]	auto[0]	auto[1]	auto[0]	139	1			T37	2		T38	5		T39	2
all_values[7]	auto[0]	auto[1]	auto[1]	69	1			T37	3		T39	5		T150	2
all_values[7]	auto[1]	auto[0]	auto[1]	191	1			T37	4		T39	2		T40	2
all_values[7]	auto[1]	auto[1]	auto[1]	159	1			T37	5		T38	3		T39	6

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal