Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1877

1

T15

6

T16

1

T30

3

auto[1]

1746

1

T4

1

T15

6

T30

7

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1954

1

T16

1

T30

8

T32

11

auto[1]

1669

1

T4

1

T15

12

T30

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2911

1

T4

1

T15

12

T16

1

auto[1]

712

1

T30

7

T32

4

T34

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	736	1			T15	5		T32	1		T33	4
valid[1]	750	1			T15	1		T30	2		T32	4
valid[2]	698	1			T4	1		T30	2		T32	2
valid[3]	720	1			T15	3		T16	1		T30	4
valid[4]	719	1			T15	3		T30	2		T32	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	127	1			T32	1		T52	1		T76	2
auto[0]	auto[0]	valid[0]	auto[1]	174	1			T15	2		T33	2		T35	1
auto[0]	auto[0]	valid[1]	auto[0]	140	1			T30	1		T32	1		T34	2
auto[0]	auto[0]	valid[1]	auto[1]	178	1			T33	2		T80	1		T105	1
auto[0]	auto[0]	valid[2]	auto[0]	134	1			T32	1		T34	1		T76	1
auto[0]	auto[0]	valid[2]	auto[1]	154	1			T30	1		T33	2		T80	2
auto[0]	auto[0]	valid[3]	auto[0]	133	1			T16	1		T34	1		T76	4
auto[0]	auto[0]	valid[3]	auto[1]	175	1			T15	3		T33	5		T35	2
auto[0]	auto[0]	valid[4]	auto[0]	108	1			T34	1		T76	1		T104	1
auto[0]	auto[0]	valid[4]	auto[1]	177	1			T15	1		T33	6		T35	1
auto[0]	auto[1]	valid[0]	auto[0]	127	1			T34	1		T52	2		T104	1
auto[0]	auto[1]	valid[0]	auto[1]	160	1			T15	3		T33	2		T35	1
auto[0]	auto[1]	valid[1]	auto[0]	119	1			T32	1		T34	1		T76	3
auto[0]	auto[1]	valid[1]	auto[1]	168	1			T15	1		T33	3		T35	1
auto[0]	auto[1]	valid[2]	auto[0]	108	1			T32	1		T76	1		T50	1
auto[0]	auto[1]	valid[2]	auto[1]	164	1			T4	1		T30	1		T33	3
auto[0]	auto[1]	valid[3]	auto[0]	115	1			T32	1		T76	1		T104	2
auto[0]	auto[1]	valid[3]	auto[1]	163	1			T33	1		T80	2		T106	1
auto[0]	auto[1]	valid[4]	auto[0]	131	1			T32	1		T34	1		T52	1
auto[0]	auto[1]	valid[4]	auto[1]	156	1			T15	2		T33	4		T35	1
auto[1]	auto[0]	valid[0]	auto[0]	82	1			T76	2		T89	1		T49	1
auto[1]	auto[0]	valid[1]	auto[0]	77	1			T89	1		T50	1		T369	1
auto[1]	auto[0]	valid[2]	auto[0]	69	1			T34	2		T76	1		T89	1
auto[1]	auto[0]	valid[3]	auto[0]	68	1			T30	1		T366	1		T50	1
auto[1]	auto[0]	valid[4]	auto[0]	81	1			T76	1		T104	1		T368	2
auto[1]	auto[1]	valid[0]	auto[0]	66	1			T76	1		T37	1		T99	2
auto[1]	auto[1]	valid[1]	auto[0]	68	1			T30	1		T32	2		T76	1
auto[1]	auto[1]	valid[2]	auto[0]	69	1			T76	1		T363	1		T368	1
auto[1]	auto[1]	valid[3]	auto[0]	66	1			T30	3		T32	1		T34	1
auto[1]	auto[1]	valid[4]	auto[0]	66	1			T30	2		T32	1		T99	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal