Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50706

1

T6

11

T16

14

T30

216

auto[1]

18264

1

T4

1

T15

12

T30

61

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50684

1

T4

1

T6

7

T15

12

auto[1]

18286

1

T6

4

T16

7

T30

81

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35903	1			T4	1		T6	8		T15	12
others[1]	5784	1			T6	1		T16	1		T30	30
others[2]	5917	1			T6	1		T16	2		T30	20
others[3]	6474	1			T6	1		T16	4		T30	15
interest[1]	3711	1			T16	1		T30	20		T32	14
interest[4]	23536	1			T4	1		T6	5		T15	12
interest[64]	11181	1			T16	3		T30	45		T31	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16875	1			T6	5		T30	69		T32	140
auto[0]	auto[0]	others[1]	2695	1			T30	14		T32	17		T34	25
auto[0]	auto[0]	others[2]	2759	1			T6	1		T16	2		T30	6
auto[0]	auto[0]	others[3]	3103	1			T6	1		T16	2		T30	7
auto[0]	auto[0]	interest[1]	1741	1			T16	1		T30	11		T32	10
auto[0]	auto[0]	interest[4]	10992	1			T6	4		T30	48		T32	90
auto[0]	auto[0]	interest[64]	5247	1			T16	2		T30	28		T31	2
auto[0]	auto[1]	others[0]	9542	1			T4	1		T15	12		T30	34
auto[0]	auto[1]	others[1]	1537	1			T30	10		T33	28		T52	2
auto[0]	auto[1]	others[2]	1530	1			T30	4		T33	37		T80	15
auto[0]	auto[1]	others[3]	1657	1			T30	1		T33	37		T52	3
auto[0]	auto[1]	interest[1]	997	1			T30	5		T33	24		T80	14
auto[0]	auto[1]	interest[4]	6307	1			T4	1		T15	12		T30	15
auto[0]	auto[1]	interest[64]	3001	1			T30	7		T33	72		T52	5
auto[1]	auto[0]	others[0]	9486	1			T6	3		T16	3		T30	44
auto[1]	auto[0]	others[1]	1552	1			T6	1		T16	1		T30	6
auto[1]	auto[0]	others[2]	1628	1			T30	10		T32	15		T34	12
auto[1]	auto[0]	others[3]	1714	1			T16	2		T30	7		T31	1
auto[1]	auto[0]	interest[1]	973	1			T30	4		T32	4		T34	9
auto[1]	auto[0]	interest[4]	6237	1			T6	1		T16	2		T30	30
auto[1]	auto[0]	interest[64]	2933	1			T16	1		T30	10		T32	25

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal