Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3341293	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4225163

1

T1

1

T2

104

T4

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4124216	1			T1	45		T2	101		T3	1
values[0x0]	1721321	1			T2	53		T4	15		T5	14
values[0x1]	1720919	1			T2	47		T4	16		T5	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2384809	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5181647

1

T1

17

T2

158

T4

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28941	1			T6	1		T11	7		T16	10
valid_sources[0x01]	28906	1			T11	12		T14	7		T16	1
valid_sources[0x02]	34648	1			T9	1		T11	11		T18	3
valid_sources[0x03]	29025	1			T2	2		T9	5		T11	7
valid_sources[0x04]	29035	1			T6	1		T11	8		T12	2
valid_sources[0x05]	28506	1			T2	2		T11	6		T16	4
valid_sources[0x06]	26877	1			T2	1		T11	11		T16	3
valid_sources[0x07]	28822	1			T2	2		T11	7		T13	12
valid_sources[0x08]	25762	1			T2	3		T4	1		T9	1
valid_sources[0x09]	26754	1			T2	1		T11	6		T12	3
valid_sources[0x0a]	28137	1			T2	1		T11	12		T18	7
valid_sources[0x0b]	27581	1			T9	4		T11	7		T15	1
valid_sources[0x0c]	31139	1			T2	6		T9	2		T11	8
valid_sources[0x0d]	27365	1			T9	7		T11	14		T15	3
valid_sources[0x0e]	27174	1			T2	1		T4	1		T6	4
valid_sources[0x0f]	32477	1			T11	8		T16	8		T18	9
valid_sources[0x10]	29785	1			T2	2		T6	2		T11	9
valid_sources[0x11]	31833	1			T2	1		T6	1		T9	1
valid_sources[0x12]	29220	1			T2	1		T11	13		T12	4
valid_sources[0x13]	44625	1			T1	2		T2	1		T9	3
valid_sources[0x14]	27507	1			T2	1		T9	7		T11	5
valid_sources[0x15]	27126	1			T2	1		T6	1		T7	1
valid_sources[0x16]	29078	1			T2	1		T11	4		T14	3
valid_sources[0x17]	30043	1			T4	1		T11	7		T13	39
valid_sources[0x18]	44447	1			T2	1		T9	1		T11	13
valid_sources[0x19]	27217	1			T6	2		T11	9		T13	17
valid_sources[0x1a]	28644	1			T11	11		T16	2		T39	4
valid_sources[0x1b]	28783	1			T9	1		T11	18		T13	1
valid_sources[0x1c]	59861	1			T2	1		T9	1		T11	8
valid_sources[0x1d]	28918	1			T2	1		T11	9		T14	6
valid_sources[0x1e]	28333	1			T2	2		T4	1		T9	1
valid_sources[0x1f]	29443	1			T2	1		T11	14		T38	1
valid_sources[0x20]	26369	1			T11	7		T16	2		T18	9
valid_sources[0x21]	27424	1			T2	2		T11	7		T13	9
valid_sources[0x22]	30333	1			T2	2		T9	3		T11	9
valid_sources[0x23]	27786	1			T2	1		T6	2		T11	6
valid_sources[0x24]	27417	1			T6	2		T11	11		T13	16
valid_sources[0x25]	28940	1			T9	1		T11	8		T38	1
valid_sources[0x26]	28090	1			T2	1		T11	3		T13	19
valid_sources[0x27]	27586	1			T6	2		T9	2		T11	7
valid_sources[0x28]	27788	1			T2	3		T11	16		T15	2
valid_sources[0x29]	26986	1			T1	1		T6	2		T11	2
valid_sources[0x2a]	31752	1			T2	2		T11	11		T13	11
valid_sources[0x2b]	28125	1			T11	8		T12	1		T13	15
valid_sources[0x2c]	26268	1			T2	2		T11	5		T16	3
valid_sources[0x2d]	26783	1			T2	3		T6	1		T9	2
valid_sources[0x2e]	28674	1			T2	1		T11	11		T12	2
valid_sources[0x2f]	28913	1			T2	1		T11	10		T13	16
valid_sources[0x30]	27780	1			T6	1		T11	7		T15	1
valid_sources[0x31]	34167	1			T2	1		T11	11		T13	9
valid_sources[0x32]	27588	1			T2	2		T4	1		T11	7
valid_sources[0x33]	26523	1			T2	1		T6	1		T11	10
valid_sources[0x34]	27654	1			T2	1		T11	10		T12	3
valid_sources[0x35]	28911	1			T2	1		T11	4		T38	1
valid_sources[0x36]	29032	1			T1	1		T2	1		T11	8
valid_sources[0x37]	28187	1			T6	3		T9	1		T11	14
valid_sources[0x38]	26021	1			T2	1		T11	6		T12	2
valid_sources[0x39]	25954	1			T6	2		T11	8		T15	1
valid_sources[0x3a]	26752	1			T2	1		T4	2		T9	1
valid_sources[0x3b]	30365	1			T2	1		T6	1		T9	1
valid_sources[0x3c]	27665	1			T2	6		T11	8		T12	2
valid_sources[0x3d]	27782	1			T6	1		T9	1		T11	14
valid_sources[0x3e]	27008	1			T2	1		T6	1		T11	12
valid_sources[0x3f]	32132	1			T1	1		T2	1		T11	13
valid_sources[0x40]	34511	1			T2	1		T9	2		T11	7
valid_sources[0x41]	31208	1			T2	1		T11	9		T13	11
valid_sources[0x42]	27089	1			T11	15		T12	1		T16	8
valid_sources[0x43]	26523	1			T2	1		T9	5		T11	12
valid_sources[0x44]	28410	1			T9	1		T11	8		T13	1
valid_sources[0x45]	29664	1			T2	2		T6	1		T11	6
valid_sources[0x46]	25913	1			T2	2		T9	4		T11	10
valid_sources[0x47]	28865	1			T11	4		T12	3		T16	3
valid_sources[0x48]	27298	1			T2	3		T6	1		T11	16
valid_sources[0x49]	31938	1			T11	10		T14	1		T16	5
valid_sources[0x4a]	28555	1			T11	13		T13	10		T15	1
valid_sources[0x4b]	30155	1			T9	4		T11	8		T13	9
valid_sources[0x4c]	26658	1			T9	1		T11	6		T13	29
valid_sources[0x4d]	25293	1			T2	2		T9	2		T11	11
valid_sources[0x4e]	28058	1			T2	1		T11	15		T12	5
valid_sources[0x4f]	28370	1			T2	2		T4	1		T9	2
valid_sources[0x50]	27444	1			T1	1		T2	1		T9	1
valid_sources[0x51]	27542	1			T6	2		T11	11		T18	7
valid_sources[0x52]	28010	1			T2	1		T4	1		T9	2
valid_sources[0x53]	26728	1			T2	1		T6	1		T11	12
valid_sources[0x54]	29145	1			T1	1		T2	1		T9	3
valid_sources[0x55]	29378	1			T2	1		T11	10		T13	5
valid_sources[0x56]	28094	1			T11	9		T13	8		T18	7
valid_sources[0x57]	26090	1			T9	2		T11	6		T16	4
valid_sources[0x58]	26822	1			T2	1		T11	7		T15	1
valid_sources[0x59]	32044	1			T6	3		T9	1		T11	8
valid_sources[0x5a]	26285	1			T11	14		T15	1		T16	11
valid_sources[0x5b]	29954	1			T11	9		T12	4		T13	49
valid_sources[0x5c]	58651	1			T11	13		T12	1		T16	8
valid_sources[0x5d]	25493	1			T2	1		T6	1		T11	10
valid_sources[0x5e]	29993	1			T9	3		T11	13		T16	2
valid_sources[0x5f]	38899	1			T2	2		T11	11		T16	8
valid_sources[0x60]	25604	1			T2	1		T4	2		T6	3
valid_sources[0x61]	29167	1			T2	1		T6	1		T11	7
valid_sources[0x62]	29764	1			T2	1		T9	1		T11	9
valid_sources[0x63]	30794	1			T2	3		T11	10		T13	16
valid_sources[0x64]	29317	1			T2	1		T11	6		T12	2
valid_sources[0x65]	33027	1			T2	2		T11	8		T15	3
valid_sources[0x66]	30686	1			T2	2		T11	10		T13	1
valid_sources[0x67]	27178	1			T1	3		T6	1		T11	6
valid_sources[0x68]	30202	1			T6	5		T11	11		T13	3
valid_sources[0x69]	29990	1			T2	2		T11	6		T16	2
valid_sources[0x6a]	27318	1			T2	1		T11	13		T12	1
valid_sources[0x6b]	42595	1			T6	2		T11	11		T16	3
valid_sources[0x6c]	32321	1			T2	1		T9	2		T11	9
valid_sources[0x6d]	29732	1			T2	1		T10	326		T11	10
valid_sources[0x6e]	26252	1			T11	6		T13	39		T16	2
valid_sources[0x6f]	27162	1			T6	1		T9	1		T11	13
valid_sources[0x70]	28561	1			T4	1		T9	1		T11	13
valid_sources[0x71]	26473	1			T9	8		T11	12		T12	1
valid_sources[0x72]	28969	1			T11	7		T18	10		T19	15
valid_sources[0x73]	28741	1			T11	12		T12	5		T13	8
valid_sources[0x74]	28153	1			T4	1		T11	7		T15	4
valid_sources[0x75]	28615	1			T2	1		T9	3		T11	15
valid_sources[0x76]	28244	1			T9	2		T11	10		T12	1
valid_sources[0x77]	44534	1			T2	2		T6	1		T11	5
valid_sources[0x78]	26958	1			T1	1		T2	1		T6	3
valid_sources[0x79]	27933	1			T4	1		T9	2		T11	18
valid_sources[0x7a]	49911	1			T1	1		T2	1		T11	5
valid_sources[0x7b]	27071	1			T9	2		T11	14		T13	3
valid_sources[0x7c]	31443	1			T11	7		T16	6		T39	8
valid_sources[0x7d]	29257	1			T11	6		T12	1		T16	7
valid_sources[0x7e]	28093	1			T1	3		T9	2		T11	7
valid_sources[0x7f]	26876	1			T11	7		T12	5		T13	5
valid_sources[0x80]	27628	1			T2	1		T11	16		T16	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1096543

1

T1

1

T2

4

T4

1

values[0x0]

all_enables

biggest_size

1576461

1

T2

53

T4

11

T5

1

values[0x1]

all_enables

biggest_size

1552159

1

T2

47

T4

12

T5

2