Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3358372

1

T1

44

T3

1

T4

8

full_word

4224131

1

T1

1

T4

24

T5

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7582113	1			T1	45		T3	1		T4	32
auto[TlIntgErrCmd]	141	1			T142	2		T143	10		T144	12
auto[TlIntgErrData]	126	1			T142	7		T143	9		T144	9
auto[TlIntgErrBoth]	123	1			T142	1		T143	11		T144	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4127146

1

T1

45

T3

1

T4

1

auto[1]

3455357

1

T4

31

T5

26

T8

22

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3030260	1			T1	44		T3	1		T5	1
auto[TlIntgErrNone]	partial	auto[1]	327753	1			T4	8		T5	23		T8	3
auto[TlIntgErrNone]	full_word	auto[0]	1096703	1			T1	1		T4	1		T8	1
auto[TlIntgErrNone]	full_word	auto[1]	3127397	1			T4	23		T5	3		T8	19
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T142	1		T143	5		T144	7
auto[TlIntgErrCmd]	partial	auto[1]	79	1			T142	1		T143	4		T144	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T218	1		T219	1		T217	2
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T143	1		T220	3		T218	1
auto[TlIntgErrData]	partial	auto[0]	67	1			T142	6		T143	7		T144	3
auto[TlIntgErrData]	partial	auto[1]	49	1			T142	1		T143	2		T144	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T144	1		T154	1		T219	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T144	1		T221	1		T222	1
auto[TlIntgErrBoth]	partial	auto[0]	57	1			T142	1		T143	2		T144	3
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T143	8		T144	5		T154	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T221	1		T215	1		T223	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T143	1		T144	1		T215	2