Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	446137372	2920424	0	0
DepthKnown_A	446137372	446003960	0	0
RvalidKnown_A	446137372	446003960	0	0
WreadyKnown_A	446137372	446003960	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	2920424	0	0
T2	1231	100	0	0
T3	1231	0	0	0
T4	8664	0	0	0
T5	984	0	0	0
T6	1927	0	0	0
T7	8259	0	0	0
T8	3152	0	0	0
T9	1273	100	0	0
T10	6964	0	0	0
T11	10787	0	0	0
T13	0	1663	0	0
T16	0	1669	0	0
T18	0	832	0	0
T19	0	832	0	0
T20	0	1663	0	0
T21	0	832	0	0
T22	0	2696	0	0
T39	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	446137372	3240435	0	0
DepthKnown_A	446137372	446003960	0	0
RvalidKnown_A	446137372	446003960	0	0
WreadyKnown_A	446137372	446003960	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	3240435	0	0
T2	1231	100	0	0
T3	1231	0	0	0
T4	8664	0	0	0
T5	984	0	0	0
T6	1927	0	0	0
T7	8259	0	0	0
T8	3152	0	0	0
T9	1273	100	0	0
T10	6964	0	0	0
T11	10787	0	0	0
T13	0	832	0	0
T16	0	838	0	0
T18	0	832	0	0
T19	0	832	0	0
T20	0	832	0	0
T21	0	832	0	0
T22	0	1355	0	0
T39	0	406	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	446137372	196965	0	0
DepthKnown_A	446137372	446003960	0	0
RvalidKnown_A	446137372	446003960	0	0
WreadyKnown_A	446137372	446003960	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	196965	0	0
T2	1231	100	0	0
T3	1231	0	0	0
T4	8664	0	0	0
T5	984	0	0	0
T6	1927	0	0	0
T7	8259	0	0	0
T8	3152	0	0	0
T9	1273	100	0	0
T10	6964	12	0	0
T11	10787	55	0	0
T26	0	8	0	0
T28	0	2	0	0
T39	0	100	0	0
T43	0	360	0	0
T44	0	589	0	0
T46	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	446137372	454496	0	0
DepthKnown_A	446137372	446003960	0	0
RvalidKnown_A	446137372	446003960	0	0
WreadyKnown_A	446137372	446003960	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	454496	0	0
T2	1231	100	0	0
T3	1231	0	0	0
T4	8664	0	0	0
T5	984	0	0	0
T6	1927	0	0	0
T7	8259	0	0	0
T8	3152	0	0	0
T9	1273	100	0	0
T10	6964	43	0	0
T11	10787	55	0	0
T26	0	39	0	0
T28	0	7	0	0
T39	0	438	0	0
T43	0	360	0	0
T44	0	589	0	0
T46	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	446137372	5901873	0	0
DepthKnown_A	446137372	446003960	0	0
RvalidKnown_A	446137372	446003960	0	0
WreadyKnown_A	446137372	446003960	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	5901873	0	0
T1	1686	45	0	0
T2	1231	1	0	0
T3	1231	1	0	0
T4	8664	32	0	0
T5	984	27	0	0
T6	1927	81	0	0
T7	8259	1	0	0
T8	3152	23	0	0
T9	1273	1	0	0
T10	6964	314	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	446137372	13261111	0	0
DepthKnown_A	446137372	446003960	0	0
RvalidKnown_A	446137372	446003960	0	0
WreadyKnown_A	446137372	446003960	0	0
gen_passthru_fifo.paramCheckPass	1151	1151	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	13261111	0	0
T1	1686	45	0	0
T2	1231	1	0	0
T3	1231	1	0	0
T4	8664	99	0	0
T5	984	27	0	0
T6	1927	81	0	0
T7	8259	1	0	0
T8	3152	23	0	0
T9	1273	1	0	0
T10	6964	1463	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446137372	446003960	0	0
T1	1686	1596	0	0
T2	1231	1172	0	0
T3	1231	1147	0	0
T4	8664	8564	0	0
T5	984	929	0	0
T6	1927	1861	0	0
T7	8259	5979	0	0
T8	3152	3099	0	0
T9	1273	1192	0	0
T10	6964	6883	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0