Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3320 |
0 |
0 |
T138 |
5682 |
353 |
0 |
0 |
T139 |
8799 |
6 |
0 |
0 |
T140 |
4550 |
207 |
0 |
0 |
T141 |
14454 |
4 |
0 |
0 |
T142 |
25429 |
1 |
0 |
0 |
T143 |
78783 |
7 |
0 |
0 |
T146 |
15598 |
207 |
0 |
0 |
T150 |
3298 |
71 |
0 |
0 |
T155 |
10571 |
8 |
0 |
0 |
T156 |
9119 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3706 |
0 |
0 |
T118 |
3313 |
6 |
0 |
0 |
T121 |
3125 |
9 |
0 |
0 |
T122 |
4502 |
6 |
0 |
0 |
T139 |
8799 |
24 |
0 |
0 |
T141 |
14454 |
16 |
0 |
0 |
T155 |
10571 |
13 |
0 |
0 |
T156 |
9119 |
13 |
0 |
0 |
T158 |
7850 |
3 |
0 |
0 |
T160 |
4641 |
8 |
0 |
0 |
T162 |
79811 |
598 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3516 |
0 |
0 |
T118 |
3313 |
1 |
0 |
0 |
T121 |
3125 |
4 |
0 |
0 |
T122 |
4502 |
11 |
0 |
0 |
T139 |
8799 |
6 |
0 |
0 |
T141 |
14454 |
16 |
0 |
0 |
T155 |
10571 |
22 |
0 |
0 |
T156 |
9119 |
7 |
0 |
0 |
T158 |
7850 |
2 |
0 |
0 |
T160 |
4641 |
4 |
0 |
0 |
T162 |
79811 |
459 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3856 |
0 |
0 |
T118 |
3313 |
7 |
0 |
0 |
T121 |
3125 |
6 |
0 |
0 |
T122 |
4502 |
14 |
0 |
0 |
T139 |
8799 |
6 |
0 |
0 |
T141 |
14454 |
48 |
0 |
0 |
T155 |
10571 |
17 |
0 |
0 |
T156 |
9119 |
15 |
0 |
0 |
T158 |
7850 |
14 |
0 |
0 |
T160 |
4641 |
3 |
0 |
0 |
T162 |
79811 |
468 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
7176 |
0 |
0 |
T118 |
3313 |
3 |
0 |
0 |
T121 |
3125 |
5 |
0 |
0 |
T139 |
8799 |
3 |
0 |
0 |
T141 |
14454 |
156 |
0 |
0 |
T146 |
15598 |
9 |
0 |
0 |
T155 |
10571 |
162 |
0 |
0 |
T156 |
9119 |
133 |
0 |
0 |
T158 |
7850 |
224 |
0 |
0 |
T160 |
4641 |
8 |
0 |
0 |
T162 |
79811 |
519 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
9070 |
0 |
0 |
T121 |
3125 |
8 |
0 |
0 |
T122 |
4502 |
10 |
0 |
0 |
T139 |
8799 |
9 |
0 |
0 |
T141 |
14454 |
138 |
0 |
0 |
T155 |
10571 |
127 |
0 |
0 |
T156 |
9119 |
22 |
0 |
0 |
T158 |
7850 |
109 |
0 |
0 |
T160 |
4641 |
112 |
0 |
0 |
T162 |
79811 |
495 |
0 |
0 |
T165 |
103646 |
333 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
8115 |
0 |
0 |
T118 |
3313 |
2 |
0 |
0 |
T122 |
4502 |
6 |
0 |
0 |
T139 |
8799 |
67 |
0 |
0 |
T141 |
14454 |
237 |
0 |
0 |
T155 |
10571 |
150 |
0 |
0 |
T156 |
9119 |
272 |
0 |
0 |
T158 |
7850 |
3 |
0 |
0 |
T160 |
4641 |
95 |
0 |
0 |
T162 |
79811 |
456 |
0 |
0 |
T165 |
103646 |
405 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
8003 |
0 |
0 |
T118 |
3313 |
13 |
0 |
0 |
T122 |
4502 |
8 |
0 |
0 |
T139 |
8799 |
85 |
0 |
0 |
T141 |
14454 |
136 |
0 |
0 |
T155 |
10571 |
133 |
0 |
0 |
T156 |
9119 |
140 |
0 |
0 |
T158 |
7850 |
146 |
0 |
0 |
T160 |
4641 |
109 |
0 |
0 |
T162 |
79811 |
538 |
0 |
0 |
T165 |
103646 |
450 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
8635 |
0 |
0 |
T118 |
3313 |
1 |
0 |
0 |
T121 |
3125 |
6 |
0 |
0 |
T122 |
4502 |
9 |
0 |
0 |
T139 |
8799 |
69 |
0 |
0 |
T141 |
14454 |
242 |
0 |
0 |
T155 |
10571 |
24 |
0 |
0 |
T156 |
9119 |
21 |
0 |
0 |
T158 |
7850 |
234 |
0 |
0 |
T162 |
79811 |
490 |
0 |
0 |
T165 |
103646 |
443 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
7907 |
0 |
0 |
T118 |
3313 |
9 |
0 |
0 |
T121 |
3125 |
6 |
0 |
0 |
T122 |
4502 |
13 |
0 |
0 |
T139 |
8799 |
92 |
0 |
0 |
T141 |
14454 |
140 |
0 |
0 |
T155 |
10571 |
138 |
0 |
0 |
T156 |
9119 |
10 |
0 |
0 |
T158 |
7850 |
134 |
0 |
0 |
T160 |
4641 |
114 |
0 |
0 |
T162 |
79811 |
511 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
8435 |
0 |
0 |
T118 |
3313 |
7 |
0 |
0 |
T121 |
3125 |
2 |
0 |
0 |
T122 |
4502 |
10 |
0 |
0 |
T139 |
8799 |
102 |
0 |
0 |
T141 |
14454 |
293 |
0 |
0 |
T155 |
10571 |
159 |
0 |
0 |
T156 |
9119 |
14 |
0 |
0 |
T158 |
7850 |
163 |
0 |
0 |
T160 |
4641 |
150 |
0 |
0 |
T162 |
79811 |
509 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
8713 |
0 |
0 |
T118 |
3313 |
5 |
0 |
0 |
T121 |
3125 |
1 |
0 |
0 |
T122 |
4502 |
13 |
0 |
0 |
T139 |
8799 |
90 |
0 |
0 |
T141 |
14454 |
110 |
0 |
0 |
T155 |
10571 |
136 |
0 |
0 |
T156 |
9119 |
129 |
0 |
0 |
T158 |
7850 |
120 |
0 |
0 |
T160 |
4641 |
96 |
0 |
0 |
T162 |
79811 |
533 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5607 |
0 |
0 |
T118 |
3313 |
9 |
0 |
0 |
T121 |
3125 |
4 |
0 |
0 |
T122 |
4502 |
9 |
0 |
0 |
T139 |
8799 |
8 |
0 |
0 |
T141 |
14454 |
54 |
0 |
0 |
T155 |
10571 |
63 |
0 |
0 |
T156 |
9119 |
144 |
0 |
0 |
T158 |
7850 |
100 |
0 |
0 |
T160 |
4641 |
38 |
0 |
0 |
T162 |
79811 |
541 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5044 |
0 |
0 |
T118 |
3313 |
8 |
0 |
0 |
T121 |
3125 |
8 |
0 |
0 |
T139 |
8799 |
51 |
0 |
0 |
T141 |
14454 |
40 |
0 |
0 |
T146 |
15598 |
8 |
0 |
0 |
T155 |
10571 |
49 |
0 |
0 |
T156 |
9119 |
74 |
0 |
0 |
T158 |
7850 |
84 |
0 |
0 |
T160 |
4641 |
54 |
0 |
0 |
T162 |
79811 |
470 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5537 |
0 |
0 |
T118 |
3313 |
9 |
0 |
0 |
T121 |
3125 |
4 |
0 |
0 |
T122 |
4502 |
10 |
0 |
0 |
T139 |
8799 |
16 |
0 |
0 |
T141 |
14454 |
59 |
0 |
0 |
T155 |
10571 |
160 |
0 |
0 |
T156 |
9119 |
54 |
0 |
0 |
T158 |
7850 |
64 |
0 |
0 |
T160 |
4641 |
50 |
0 |
0 |
T162 |
79811 |
491 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5638 |
0 |
0 |
T121 |
3125 |
11 |
0 |
0 |
T122 |
4502 |
8 |
0 |
0 |
T139 |
8799 |
65 |
0 |
0 |
T141 |
14454 |
74 |
0 |
0 |
T155 |
10571 |
53 |
0 |
0 |
T156 |
9119 |
64 |
0 |
0 |
T158 |
7850 |
37 |
0 |
0 |
T160 |
4641 |
47 |
0 |
0 |
T162 |
79811 |
497 |
0 |
0 |
T165 |
103646 |
415 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5162 |
0 |
0 |
T118 |
3313 |
16 |
0 |
0 |
T121 |
3125 |
8 |
0 |
0 |
T122 |
4502 |
7 |
0 |
0 |
T139 |
8799 |
31 |
0 |
0 |
T141 |
14454 |
57 |
0 |
0 |
T155 |
10571 |
75 |
0 |
0 |
T156 |
9119 |
71 |
0 |
0 |
T158 |
7850 |
56 |
0 |
0 |
T160 |
4641 |
4 |
0 |
0 |
T162 |
79811 |
557 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5463 |
0 |
0 |
T118 |
3313 |
3 |
0 |
0 |
T122 |
4502 |
3 |
0 |
0 |
T141 |
14454 |
18 |
0 |
0 |
T146 |
15598 |
1 |
0 |
0 |
T155 |
10571 |
76 |
0 |
0 |
T156 |
9119 |
85 |
0 |
0 |
T158 |
7850 |
119 |
0 |
0 |
T160 |
4641 |
56 |
0 |
0 |
T162 |
79811 |
456 |
0 |
0 |
T165 |
103646 |
397 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5549 |
0 |
0 |
T118 |
3313 |
19 |
0 |
0 |
T122 |
4502 |
10 |
0 |
0 |
T139 |
8799 |
10 |
0 |
0 |
T141 |
14454 |
81 |
0 |
0 |
T155 |
10571 |
48 |
0 |
0 |
T156 |
9119 |
50 |
0 |
0 |
T158 |
7850 |
71 |
0 |
0 |
T160 |
4641 |
9 |
0 |
0 |
T162 |
79811 |
505 |
0 |
0 |
T165 |
103646 |
449 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5855 |
0 |
0 |
T122 |
4502 |
13 |
0 |
0 |
T139 |
8799 |
72 |
0 |
0 |
T141 |
14454 |
74 |
0 |
0 |
T144 |
103119 |
1133 |
0 |
0 |
T155 |
10571 |
77 |
0 |
0 |
T156 |
9119 |
62 |
0 |
0 |
T158 |
7850 |
66 |
0 |
0 |
T160 |
4641 |
9 |
0 |
0 |
T162 |
79811 |
547 |
0 |
0 |
T165 |
103646 |
374 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5268 |
0 |
0 |
T118 |
3313 |
2 |
0 |
0 |
T121 |
3125 |
11 |
0 |
0 |
T122 |
4502 |
7 |
0 |
0 |
T139 |
8799 |
18 |
0 |
0 |
T141 |
14454 |
65 |
0 |
0 |
T155 |
10571 |
57 |
0 |
0 |
T156 |
9119 |
7 |
0 |
0 |
T160 |
4641 |
2 |
0 |
0 |
T162 |
79811 |
542 |
0 |
0 |
T165 |
103646 |
463 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5485 |
0 |
0 |
T118 |
3313 |
3 |
0 |
0 |
T122 |
4502 |
4 |
0 |
0 |
T139 |
8799 |
54 |
0 |
0 |
T141 |
14454 |
77 |
0 |
0 |
T155 |
10571 |
24 |
0 |
0 |
T156 |
9119 |
27 |
0 |
0 |
T158 |
7850 |
48 |
0 |
0 |
T160 |
4641 |
41 |
0 |
0 |
T162 |
79811 |
482 |
0 |
0 |
T165 |
103646 |
392 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5446 |
0 |
0 |
T118 |
3313 |
11 |
0 |
0 |
T121 |
3125 |
9 |
0 |
0 |
T122 |
4502 |
8 |
0 |
0 |
T139 |
8799 |
77 |
0 |
0 |
T141 |
14454 |
105 |
0 |
0 |
T155 |
10571 |
105 |
0 |
0 |
T156 |
9119 |
53 |
0 |
0 |
T158 |
7850 |
4 |
0 |
0 |
T160 |
4641 |
48 |
0 |
0 |
T162 |
79811 |
505 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5766 |
0 |
0 |
T118 |
3313 |
8 |
0 |
0 |
T121 |
3125 |
10 |
0 |
0 |
T122 |
4502 |
19 |
0 |
0 |
T139 |
8799 |
37 |
0 |
0 |
T141 |
14454 |
191 |
0 |
0 |
T155 |
10571 |
65 |
0 |
0 |
T156 |
9119 |
57 |
0 |
0 |
T158 |
7850 |
76 |
0 |
0 |
T160 |
4641 |
8 |
0 |
0 |
T162 |
79811 |
505 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5909 |
0 |
0 |
T118 |
3313 |
9 |
0 |
0 |
T122 |
4502 |
15 |
0 |
0 |
T139 |
8799 |
16 |
0 |
0 |
T141 |
14454 |
140 |
0 |
0 |
T155 |
10571 |
57 |
0 |
0 |
T156 |
9119 |
10 |
0 |
0 |
T158 |
7850 |
104 |
0 |
0 |
T160 |
4641 |
8 |
0 |
0 |
T162 |
79811 |
556 |
0 |
0 |
T165 |
103646 |
532 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5363 |
0 |
0 |
T118 |
3313 |
7 |
0 |
0 |
T121 |
3125 |
3 |
0 |
0 |
T122 |
4502 |
17 |
0 |
0 |
T139 |
8799 |
40 |
0 |
0 |
T141 |
14454 |
135 |
0 |
0 |
T155 |
10571 |
112 |
0 |
0 |
T156 |
9119 |
100 |
0 |
0 |
T158 |
7850 |
67 |
0 |
0 |
T160 |
4641 |
27 |
0 |
0 |
T162 |
79811 |
431 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5605 |
0 |
0 |
T118 |
3313 |
6 |
0 |
0 |
T121 |
3125 |
9 |
0 |
0 |
T122 |
4502 |
12 |
0 |
0 |
T139 |
8799 |
81 |
0 |
0 |
T141 |
14454 |
22 |
0 |
0 |
T155 |
10571 |
67 |
0 |
0 |
T156 |
9119 |
102 |
0 |
0 |
T158 |
7850 |
45 |
0 |
0 |
T160 |
4641 |
6 |
0 |
0 |
T162 |
79811 |
502 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5640 |
0 |
0 |
T118 |
3313 |
9 |
0 |
0 |
T121 |
3125 |
9 |
0 |
0 |
T122 |
4502 |
10 |
0 |
0 |
T139 |
8799 |
9 |
0 |
0 |
T141 |
14454 |
71 |
0 |
0 |
T155 |
10571 |
13 |
0 |
0 |
T156 |
9119 |
67 |
0 |
0 |
T158 |
7850 |
56 |
0 |
0 |
T160 |
4641 |
21 |
0 |
0 |
T162 |
79811 |
512 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5358 |
0 |
0 |
T118 |
3313 |
4 |
0 |
0 |
T121 |
3125 |
4 |
0 |
0 |
T122 |
4502 |
9 |
0 |
0 |
T139 |
8799 |
60 |
0 |
0 |
T141 |
14454 |
102 |
0 |
0 |
T155 |
10571 |
109 |
0 |
0 |
T156 |
9119 |
14 |
0 |
0 |
T158 |
7850 |
48 |
0 |
0 |
T160 |
4641 |
6 |
0 |
0 |
T162 |
79811 |
473 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5233 |
0 |
0 |
T118 |
3313 |
16 |
0 |
0 |
T121 |
3125 |
10 |
0 |
0 |
T122 |
4502 |
11 |
0 |
0 |
T139 |
8799 |
84 |
0 |
0 |
T141 |
14454 |
91 |
0 |
0 |
T155 |
10571 |
133 |
0 |
0 |
T156 |
9119 |
9 |
0 |
0 |
T158 |
7850 |
3 |
0 |
0 |
T162 |
79811 |
541 |
0 |
0 |
T165 |
103646 |
370 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5614 |
0 |
0 |
T118 |
3313 |
6 |
0 |
0 |
T121 |
3125 |
7 |
0 |
0 |
T122 |
4502 |
12 |
0 |
0 |
T139 |
8799 |
55 |
0 |
0 |
T141 |
14454 |
187 |
0 |
0 |
T155 |
10571 |
59 |
0 |
0 |
T156 |
9119 |
18 |
0 |
0 |
T158 |
7850 |
83 |
0 |
0 |
T160 |
4641 |
1 |
0 |
0 |
T162 |
79811 |
498 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5561 |
0 |
0 |
T118 |
3313 |
6 |
0 |
0 |
T121 |
3125 |
1 |
0 |
0 |
T122 |
4502 |
14 |
0 |
0 |
T139 |
8799 |
27 |
0 |
0 |
T141 |
14454 |
92 |
0 |
0 |
T155 |
10571 |
62 |
0 |
0 |
T156 |
9119 |
67 |
0 |
0 |
T158 |
7850 |
6 |
0 |
0 |
T160 |
4641 |
36 |
0 |
0 |
T162 |
79811 |
525 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5294 |
0 |
0 |
T118 |
3313 |
8 |
0 |
0 |
T122 |
4502 |
14 |
0 |
0 |
T139 |
8799 |
1 |
0 |
0 |
T141 |
14454 |
152 |
0 |
0 |
T155 |
10571 |
79 |
0 |
0 |
T156 |
9119 |
23 |
0 |
0 |
T158 |
7850 |
38 |
0 |
0 |
T160 |
4641 |
34 |
0 |
0 |
T162 |
79811 |
492 |
0 |
0 |
T165 |
103646 |
420 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5233 |
0 |
0 |
T118 |
3313 |
1 |
0 |
0 |
T121 |
3125 |
4 |
0 |
0 |
T122 |
4502 |
11 |
0 |
0 |
T139 |
8799 |
28 |
0 |
0 |
T141 |
14454 |
143 |
0 |
0 |
T155 |
10571 |
67 |
0 |
0 |
T156 |
9119 |
16 |
0 |
0 |
T158 |
7850 |
67 |
0 |
0 |
T160 |
4641 |
29 |
0 |
0 |
T162 |
79811 |
505 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5245 |
0 |
0 |
T118 |
3313 |
5 |
0 |
0 |
T121 |
3125 |
3 |
0 |
0 |
T122 |
4502 |
9 |
0 |
0 |
T139 |
8799 |
22 |
0 |
0 |
T141 |
14454 |
58 |
0 |
0 |
T155 |
10571 |
59 |
0 |
0 |
T156 |
9119 |
67 |
0 |
0 |
T158 |
7850 |
64 |
0 |
0 |
T160 |
4641 |
52 |
0 |
0 |
T162 |
79811 |
435 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5262 |
0 |
0 |
T118 |
3313 |
11 |
0 |
0 |
T121 |
3125 |
5 |
0 |
0 |
T122 |
4502 |
9 |
0 |
0 |
T139 |
8799 |
29 |
0 |
0 |
T141 |
14454 |
36 |
0 |
0 |
T155 |
10571 |
71 |
0 |
0 |
T156 |
9119 |
21 |
0 |
0 |
T158 |
7850 |
51 |
0 |
0 |
T160 |
4641 |
48 |
0 |
0 |
T162 |
79811 |
464 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3587 |
0 |
0 |
T118 |
3313 |
10 |
0 |
0 |
T121 |
3125 |
4 |
0 |
0 |
T122 |
4502 |
4 |
0 |
0 |
T139 |
8799 |
23 |
0 |
0 |
T141 |
14454 |
35 |
0 |
0 |
T155 |
10571 |
12 |
0 |
0 |
T156 |
9119 |
21 |
0 |
0 |
T158 |
7850 |
6 |
0 |
0 |
T160 |
4641 |
6 |
0 |
0 |
T162 |
79811 |
430 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3833 |
0 |
0 |
T118 |
3313 |
8 |
0 |
0 |
T122 |
4502 |
8 |
0 |
0 |
T139 |
8799 |
5 |
0 |
0 |
T141 |
14454 |
36 |
0 |
0 |
T155 |
10571 |
18 |
0 |
0 |
T156 |
9119 |
20 |
0 |
0 |
T158 |
7850 |
21 |
0 |
0 |
T160 |
4641 |
4 |
0 |
0 |
T162 |
79811 |
429 |
0 |
0 |
T165 |
103646 |
466 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3954 |
0 |
0 |
T118 |
3313 |
9 |
0 |
0 |
T121 |
3125 |
3 |
0 |
0 |
T122 |
4502 |
16 |
0 |
0 |
T139 |
8799 |
5 |
0 |
0 |
T141 |
14454 |
34 |
0 |
0 |
T155 |
10571 |
35 |
0 |
0 |
T156 |
9119 |
24 |
0 |
0 |
T158 |
7850 |
4 |
0 |
0 |
T160 |
4641 |
2 |
0 |
0 |
T162 |
79811 |
522 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3546 |
0 |
0 |
T118 |
3313 |
4 |
0 |
0 |
T121 |
3125 |
12 |
0 |
0 |
T122 |
4502 |
5 |
0 |
0 |
T141 |
14454 |
24 |
0 |
0 |
T155 |
10571 |
26 |
0 |
0 |
T156 |
9119 |
15 |
0 |
0 |
T158 |
7850 |
8 |
0 |
0 |
T160 |
4641 |
9 |
0 |
0 |
T162 |
79811 |
458 |
0 |
0 |
T165 |
103646 |
388 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
4181 |
0 |
0 |
T118 |
3313 |
5 |
0 |
0 |
T121 |
3125 |
7 |
0 |
0 |
T122 |
4502 |
16 |
0 |
0 |
T139 |
8799 |
6 |
0 |
0 |
T141 |
14454 |
42 |
0 |
0 |
T155 |
10571 |
18 |
0 |
0 |
T156 |
9119 |
24 |
0 |
0 |
T158 |
7850 |
19 |
0 |
0 |
T160 |
4641 |
16 |
0 |
0 |
T162 |
79811 |
507 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
5508 |
0 |
0 |
T34 |
130155 |
30 |
0 |
0 |
T37 |
0 |
29 |
0 |
0 |
T90 |
0 |
19 |
0 |
0 |
T116 |
0 |
41 |
0 |
0 |
T181 |
0 |
30 |
0 |
0 |
T182 |
0 |
31 |
0 |
0 |
T183 |
0 |
51 |
0 |
0 |
T184 |
0 |
27 |
0 |
0 |
T185 |
0 |
7 |
0 |
0 |
T186 |
0 |
45 |
0 |
0 |
T187 |
15582 |
0 |
0 |
0 |
T188 |
255947 |
0 |
0 |
0 |
T189 |
1097 |
0 |
0 |
0 |
T190 |
180371 |
0 |
0 |
0 |
T191 |
1318 |
0 |
0 |
0 |
T192 |
3036 |
0 |
0 |
0 |
T193 |
1374 |
0 |
0 |
0 |
T194 |
12113 |
0 |
0 |
0 |
T195 |
232373 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3863 |
0 |
0 |
T118 |
3313 |
14 |
0 |
0 |
T122 |
4502 |
9 |
0 |
0 |
T139 |
8799 |
1 |
0 |
0 |
T141 |
14454 |
25 |
0 |
0 |
T155 |
10571 |
22 |
0 |
0 |
T156 |
9119 |
17 |
0 |
0 |
T158 |
7850 |
20 |
0 |
0 |
T160 |
4641 |
5 |
0 |
0 |
T162 |
79811 |
533 |
0 |
0 |
T165 |
103646 |
474 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3884 |
0 |
0 |
T118 |
3313 |
10 |
0 |
0 |
T121 |
3125 |
8 |
0 |
0 |
T122 |
4502 |
13 |
0 |
0 |
T139 |
8799 |
14 |
0 |
0 |
T141 |
14454 |
26 |
0 |
0 |
T155 |
10571 |
23 |
0 |
0 |
T156 |
9119 |
9 |
0 |
0 |
T158 |
7850 |
13 |
0 |
0 |
T160 |
4641 |
2 |
0 |
0 |
T162 |
79811 |
499 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3470 |
0 |
0 |
T118 |
3313 |
12 |
0 |
0 |
T122 |
4502 |
9 |
0 |
0 |
T139 |
8799 |
14 |
0 |
0 |
T141 |
14454 |
26 |
0 |
0 |
T155 |
10571 |
9 |
0 |
0 |
T156 |
9119 |
17 |
0 |
0 |
T158 |
7850 |
5 |
0 |
0 |
T160 |
4641 |
8 |
0 |
0 |
T162 |
79811 |
438 |
0 |
0 |
T165 |
103646 |
366 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3661 |
0 |
0 |
T118 |
3313 |
10 |
0 |
0 |
T122 |
4502 |
3 |
0 |
0 |
T141 |
14454 |
33 |
0 |
0 |
T144 |
103119 |
139 |
0 |
0 |
T146 |
15598 |
1 |
0 |
0 |
T155 |
10571 |
7 |
0 |
0 |
T156 |
9119 |
16 |
0 |
0 |
T158 |
7850 |
13 |
0 |
0 |
T162 |
79811 |
507 |
0 |
0 |
T165 |
103646 |
446 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3731 |
0 |
0 |
T118 |
3313 |
9 |
0 |
0 |
T121 |
3125 |
9 |
0 |
0 |
T122 |
4502 |
24 |
0 |
0 |
T139 |
8799 |
12 |
0 |
0 |
T141 |
14454 |
29 |
0 |
0 |
T155 |
10571 |
17 |
0 |
0 |
T156 |
9119 |
18 |
0 |
0 |
T158 |
7850 |
9 |
0 |
0 |
T160 |
4641 |
3 |
0 |
0 |
T162 |
79811 |
480 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3585 |
0 |
0 |
T118 |
3313 |
4 |
0 |
0 |
T121 |
3125 |
3 |
0 |
0 |
T122 |
4502 |
8 |
0 |
0 |
T139 |
8799 |
9 |
0 |
0 |
T141 |
14454 |
20 |
0 |
0 |
T155 |
10571 |
13 |
0 |
0 |
T156 |
9119 |
11 |
0 |
0 |
T158 |
7850 |
3 |
0 |
0 |
T160 |
4641 |
6 |
0 |
0 |
T162 |
79811 |
508 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
4039 |
0 |
0 |
T118 |
3313 |
6 |
0 |
0 |
T122 |
4502 |
5 |
0 |
0 |
T139 |
8799 |
3 |
0 |
0 |
T141 |
14454 |
28 |
0 |
0 |
T144 |
103119 |
264 |
0 |
0 |
T155 |
10571 |
8 |
0 |
0 |
T156 |
9119 |
9 |
0 |
0 |
T158 |
7850 |
8 |
0 |
0 |
T162 |
79811 |
514 |
0 |
0 |
T165 |
103646 |
448 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3589 |
0 |
0 |
T118 |
3313 |
9 |
0 |
0 |
T121 |
3125 |
12 |
0 |
0 |
T122 |
4502 |
7 |
0 |
0 |
T139 |
8799 |
2 |
0 |
0 |
T141 |
14454 |
23 |
0 |
0 |
T155 |
10571 |
11 |
0 |
0 |
T156 |
9119 |
19 |
0 |
0 |
T158 |
7850 |
9 |
0 |
0 |
T162 |
79811 |
503 |
0 |
0 |
T165 |
103646 |
423 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
4032 |
0 |
0 |
T118 |
3313 |
9 |
0 |
0 |
T121 |
3125 |
6 |
0 |
0 |
T122 |
4502 |
10 |
0 |
0 |
T139 |
8799 |
20 |
0 |
0 |
T141 |
14454 |
70 |
0 |
0 |
T155 |
10571 |
19 |
0 |
0 |
T156 |
9119 |
32 |
0 |
0 |
T158 |
7850 |
7 |
0 |
0 |
T160 |
4641 |
8 |
0 |
0 |
T162 |
79811 |
461 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3613 |
0 |
0 |
T118 |
3313 |
10 |
0 |
0 |
T121 |
3125 |
1 |
0 |
0 |
T122 |
4502 |
10 |
0 |
0 |
T139 |
8799 |
4 |
0 |
0 |
T141 |
14454 |
25 |
0 |
0 |
T155 |
10571 |
14 |
0 |
0 |
T156 |
9119 |
26 |
0 |
0 |
T158 |
7850 |
12 |
0 |
0 |
T162 |
79811 |
487 |
0 |
0 |
T165 |
103646 |
437 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3659 |
0 |
0 |
T118 |
3313 |
7 |
0 |
0 |
T122 |
4502 |
7 |
0 |
0 |
T141 |
14454 |
13 |
0 |
0 |
T144 |
103119 |
139 |
0 |
0 |
T155 |
10571 |
23 |
0 |
0 |
T156 |
9119 |
17 |
0 |
0 |
T158 |
7850 |
5 |
0 |
0 |
T160 |
4641 |
2 |
0 |
0 |
T162 |
79811 |
538 |
0 |
0 |
T165 |
103646 |
461 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3684 |
0 |
0 |
T118 |
3313 |
5 |
0 |
0 |
T122 |
4502 |
8 |
0 |
0 |
T141 |
14454 |
25 |
0 |
0 |
T144 |
103119 |
132 |
0 |
0 |
T155 |
10571 |
12 |
0 |
0 |
T156 |
9119 |
8 |
0 |
0 |
T158 |
7850 |
5 |
0 |
0 |
T160 |
4641 |
1 |
0 |
0 |
T162 |
79811 |
535 |
0 |
0 |
T165 |
103646 |
353 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3669 |
0 |
0 |
T118 |
3313 |
2 |
0 |
0 |
T122 |
4502 |
16 |
0 |
0 |
T139 |
8799 |
2 |
0 |
0 |
T141 |
14454 |
18 |
0 |
0 |
T155 |
10571 |
23 |
0 |
0 |
T156 |
9119 |
22 |
0 |
0 |
T158 |
7850 |
3 |
0 |
0 |
T160 |
4641 |
5 |
0 |
0 |
T162 |
79811 |
524 |
0 |
0 |
T165 |
103646 |
393 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3794 |
0 |
0 |
T118 |
3313 |
2 |
0 |
0 |
T121 |
3125 |
2 |
0 |
0 |
T122 |
4502 |
7 |
0 |
0 |
T139 |
8799 |
14 |
0 |
0 |
T141 |
14454 |
23 |
0 |
0 |
T155 |
10571 |
15 |
0 |
0 |
T156 |
9119 |
13 |
0 |
0 |
T158 |
7850 |
14 |
0 |
0 |
T162 |
79811 |
538 |
0 |
0 |
T165 |
103646 |
447 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3575 |
0 |
0 |
T118 |
3313 |
4 |
0 |
0 |
T122 |
4502 |
8 |
0 |
0 |
T139 |
8799 |
5 |
0 |
0 |
T141 |
14454 |
19 |
0 |
0 |
T155 |
10571 |
6 |
0 |
0 |
T156 |
9119 |
11 |
0 |
0 |
T158 |
7850 |
9 |
0 |
0 |
T160 |
4641 |
5 |
0 |
0 |
T162 |
79811 |
467 |
0 |
0 |
T165 |
103646 |
460 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
446137372 |
3545 |
0 |
0 |
T118 |
3313 |
2 |
0 |
0 |
T121 |
3125 |
4 |
0 |
0 |
T122 |
4502 |
9 |
0 |
0 |
T141 |
14454 |
27 |
0 |
0 |
T155 |
10571 |
21 |
0 |
0 |
T156 |
9119 |
15 |
0 |
0 |
T158 |
7850 |
7 |
0 |
0 |
T160 |
4641 |
3 |
0 |
0 |
T162 |
79811 |
432 |
0 |
0 |
T165 |
103646 |
442 |
0 |
0 |