Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2544404	1			T1	1		T2	1		T4	1
all_values[1]	2544404	1			T1	1		T2	1		T4	1
all_values[2]	2544404	1			T1	1		T2	1		T4	1
all_values[3]	2544404	1			T1	1		T2	1		T4	1
all_values[4]	2544404	1			T1	1		T2	1		T4	1
all_values[5]	2544404	1			T1	1		T2	1		T4	1
all_values[6]	2544404	1			T1	1		T2	1		T4	1
all_values[7]	2544404	1			T1	1		T2	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19781168

1

T1

8

T2

8

T4

8

auto[1]

574064

1

T22

36

T34

6709

T35

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20329538

1

T1

8

T2

8

T4

8

auto[1]

25694

1

T22

30

T73

13

T51

8

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2410316	1			T1	1		T2	1		T4	1
all_values[0]	auto[0]	auto[1]	11639	1			T22	2		T73	9		T51	4
all_values[0]	auto[1]	auto[0]	121530	1			T22	2		T34	8		T35	5
all_values[0]	auto[1]	auto[1]	919	1			T22	4		T34	6		T180	52
all_values[1]	auto[0]	auto[0]	2494132	1			T1	1		T2	1		T4	1
all_values[1]	auto[0]	auto[1]	7537	1			T22	2		T73	4		T51	4
all_values[1]	auto[1]	auto[0]	42467	1			T22	3		T34	1295		T35	3
all_values[1]	auto[1]	auto[1]	268	1			T34	36		T35	1		T37	2
all_values[2]	auto[0]	auto[0]	2493628	1			T1	1		T2	1		T4	1
all_values[2]	auto[0]	auto[1]	3011	1			T22	1		T93	11		T34	5
all_values[2]	auto[1]	auto[0]	47393	1			T34	1320		T35	2		T37	3
all_values[2]	auto[1]	auto[1]	372	1			T22	4		T34	17		T37	2
all_values[3]	auto[0]	auto[0]	2418067	1			T1	1		T2	1		T4	1
all_values[3]	auto[0]	auto[1]	202	1			T34	7		T37	1		T180	2
all_values[3]	auto[1]	auto[0]	125924	1			T22	3		T34	12		T35	2
all_values[3]	auto[1]	auto[1]	211	1			T22	1		T34	3		T35	4
all_values[4]	auto[0]	auto[0]	2493746	1			T1	1		T2	1		T4	1
all_values[4]	auto[0]	auto[1]	172	1			T22	2		T34	2		T35	1
all_values[4]	auto[1]	auto[0]	50293	1			T34	7		T35	2		T37	7
all_values[4]	auto[1]	auto[1]	193	1			T22	1		T34	2		T35	3
all_values[5]	auto[0]	auto[0]	2499399	1			T1	1		T2	1		T4	1
all_values[5]	auto[0]	auto[1]	183	1			T22	2		T34	6		T35	1
all_values[5]	auto[1]	auto[0]	44626	1			T22	2		T34	1329		T35	1
all_values[5]	auto[1]	auto[1]	196	1			T22	2		T34	6		T35	4
all_values[6]	auto[0]	auto[0]	2438600	1			T1	1		T2	1		T4	1
all_values[6]	auto[0]	auto[1]	193	1			T22	1		T34	8		T35	3
all_values[6]	auto[1]	auto[0]	105422	1			T22	5		T34	1328		T35	1
all_values[6]	auto[1]	auto[1]	189	1			T22	3		T34	6		T35	2
all_values[7]	auto[0]	auto[0]	2510133	1			T1	1		T2	1		T4	1
all_values[7]	auto[0]	auto[1]	210	1			T22	2		T34	5		T35	1
all_values[7]	auto[1]	auto[0]	33862	1			T22	3		T34	1326		T35	3
all_values[7]	auto[1]	auto[1]	199	1			T22	3		T34	8		T35	4