Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total tests in report: 1150
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
64.77 64.77 92.10 92.10 79.82 79.82 83.27 83.27 26.67 26.67 89.01 89.01 71.57 71.57 10.94 10.94 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.900575929
73.71 8.94 94.10 2.00 83.84 4.03 83.27 0.00 60.00 33.33 91.64 2.64 78.57 7.00 24.55 13.61 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2521432417
78.41 4.70 96.31 2.21 87.83 3.99 86.02 2.76 68.89 8.89 94.69 3.04 84.29 5.71 30.84 6.29 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.3891022778
82.21 3.80 96.62 0.31 88.41 0.57 86.02 0.00 82.22 13.33 95.23 0.54 84.29 0.00 42.67 11.83 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.3656280550
84.89 2.68 96.89 0.27 88.75 0.35 86.12 0.10 91.11 8.89 95.55 0.32 84.43 0.14 51.39 8.71 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.45805882
86.72 1.82 97.29 0.41 89.87 1.12 88.39 2.26 91.11 0.00 95.97 0.42 84.57 0.14 59.80 8.42 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.2203783089
88.28 1.56 97.29 0.00 90.00 0.12 88.78 0.39 91.11 0.00 96.01 0.03 93.29 8.71 61.49 1.68 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2565302348
89.37 1.09 97.30 0.01 90.12 0.12 88.78 0.00 91.11 0.00 96.04 0.03 93.29 0.00 68.96 7.48 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.3215344951
90.39 1.02 97.56 0.25 90.62 0.50 91.14 2.36 93.33 2.22 96.41 0.37 93.43 0.14 70.25 1.29 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.1245615084
91.20 0.81 98.12 0.57 90.63 0.01 95.87 4.72 93.33 0.00 96.75 0.34 93.43 0.00 70.25 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.3505066791
91.88 0.68 98.12 0.00 90.63 0.00 95.87 0.00 93.33 0.00 96.75 0.00 93.43 0.00 75.00 4.75 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.1463062160
92.51 0.63 98.12 0.00 90.63 0.00 95.87 0.00 93.33 0.00 96.75 0.00 93.43 0.00 79.41 4.41 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.3062779890
92.93 0.42 98.12 0.00 90.63 0.00 95.87 0.00 93.33 0.00 96.75 0.00 93.43 0.00 82.38 2.97 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.3686586666
93.30 0.37 98.13 0.01 90.67 0.04 98.03 2.17 93.33 0.00 96.77 0.02 93.57 0.14 82.62 0.25 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.3383737834
93.68 0.37 98.31 0.18 91.36 0.70 98.03 0.00 93.33 0.00 97.09 0.32 94.14 0.57 83.47 0.84 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.1054844158
94.00 0.32 98.31 0.00 91.39 0.02 98.03 0.00 93.33 0.00 97.11 0.02 94.14 0.00 85.69 2.23 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.3537090356
94.28 0.28 98.31 0.00 91.39 0.00 98.03 0.00 93.33 0.00 97.11 0.00 94.14 0.00 87.67 1.98 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.3354435036
94.51 0.23 98.31 0.00 92.53 1.14 98.03 0.00 93.33 0.00 97.11 0.00 94.14 0.00 88.12 0.45 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.3640094670
94.72 0.21 98.31 0.00 92.54 0.01 98.03 0.00 93.33 0.00 97.11 0.00 94.14 0.00 89.55 1.44 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.4148749156
94.91 0.19 98.31 0.00 92.54 0.00 98.03 0.00 93.33 0.00 97.11 0.00 94.29 0.14 90.74 1.19 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.4275134425
95.08 0.17 98.32 0.01 92.64 0.10 98.03 0.00 93.33 0.00 97.12 0.02 94.29 0.00 91.83 1.09 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3819148204
95.22 0.14 98.32 0.00 92.64 0.00 98.03 0.00 93.33 0.00 97.12 0.00 95.29 1.00 91.83 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3031428542
95.37 0.14 98.32 0.00 92.64 0.00 98.03 0.00 93.33 0.00 97.12 0.00 95.29 0.00 92.82 0.99 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3801176326
95.49 0.12 98.32 0.00 92.64 0.00 98.03 0.00 93.33 0.00 97.12 0.00 95.29 0.00 93.66 0.84 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.1166953981
95.60 0.12 98.32 0.00 93.28 0.63 98.03 0.00 93.33 0.00 97.12 0.00 95.29 0.00 93.86 0.20 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3683858227
95.70 0.10 98.37 0.06 93.44 0.16 98.43 0.39 93.33 0.00 97.21 0.08 95.29 0.00 93.86 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.371657099
95.80 0.10 98.37 0.00 93.49 0.05 98.43 0.00 93.33 0.00 97.21 0.00 95.29 0.00 94.50 0.64 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.1002131028
95.90 0.10 98.37 0.00 93.49 0.00 98.43 0.00 93.33 0.00 97.21 0.00 95.29 0.00 95.20 0.69 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.113809247
95.99 0.09 98.37 0.00 93.69 0.20 98.43 0.00 93.33 0.00 97.23 0.02 95.29 0.00 95.59 0.40 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.2229900959
96.07 0.08 98.37 0.00 93.69 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.29 0.00 96.14 0.54 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.2875462208
96.12 0.06 98.37 0.00 93.69 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.29 0.00 96.53 0.40 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.4190850603
96.17 0.05 98.37 0.00 93.69 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.29 0.00 96.88 0.35 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.1373971567
96.22 0.04 98.37 0.00 93.69 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.29 0.00 97.18 0.30 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.2382400560
96.26 0.04 98.37 0.00 93.69 0.00 98.43 0.00 93.33 0.00 97.23 0.00 95.43 0.14 97.33 0.15 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.4240568060
96.29 0.04 98.40 0.03 93.72 0.04 98.62 0.20 93.33 0.00 97.23 0.00 95.43 0.00 97.33 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.3920094789
96.33 0.03 98.40 0.00 93.90 0.17 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 97.38 0.05 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.3771806334
96.35 0.03 98.40 0.00 93.95 0.05 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 97.52 0.15 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1315152119
96.38 0.02 98.44 0.04 93.95 0.00 98.62 0.00 93.33 0.00 97.26 0.03 95.43 0.00 97.62 0.10 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2585973903
96.40 0.02 98.44 0.00 93.95 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 97.77 0.15 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.2653564111
96.42 0.02 98.44 0.00 93.95 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 97.92 0.15 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.3870575859
96.44 0.02 98.44 0.00 93.95 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.07 0.15 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.2683610794
96.46 0.02 98.44 0.00 93.95 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.22 0.15 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.945286151
96.48 0.01 98.44 0.00 93.95 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.32 0.10 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.4172433616
96.49 0.01 98.44 0.00 93.95 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.42 0.10 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.2551457064
96.51 0.01 98.44 0.00 93.95 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.51 0.10 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.3405572050
96.52 0.01 98.44 0.00 93.95 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.61 0.10 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.1842222081
96.53 0.01 98.44 0.00 93.95 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.71 0.10 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.687479228
96.55 0.01 98.44 0.00 93.95 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.81 0.10 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.2859912632
96.56 0.01 98.44 0.00 93.95 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.91 0.10 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.393519201
96.57 0.01 98.44 0.00 93.96 0.01 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.480960348
96.58 0.01 98.44 0.00 94.01 0.05 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.96 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.4154259079
96.59 0.01 98.44 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.42773364
96.59 0.01 98.44 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1268006438
96.60 0.01 98.44 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.4290474426
96.61 0.01 98.44 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.4279347940
96.61 0.01 98.44 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.3958234793
96.62 0.01 98.44 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.2178876672
96.63 0.01 98.44 0.00 94.04 0.02 98.62 0.00 93.33 0.00 97.28 0.02 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.2672385824
96.63 0.01 98.44 0.00 94.06 0.02 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3445642915
96.63 0.01 98.44 0.00 94.07 0.01 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.3485102652
96.63 0.01 98.44 0.00 94.08 0.01 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.3955965965

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2879674654
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3291634061
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2104371719
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.1991795799
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3179200655
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3796973177
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1928501289
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3108590477
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3562485868
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2558291911
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1360621730
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.247238274
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.1580593231
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.701510721
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.4168076952
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2647555932
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1761173665
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1606253793
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.4147615364
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1093991330
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.1273185997
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2549200055
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3141989273
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.4182563650
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/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.390751686
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.2064791387
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1400778363
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2869532075
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2512560701
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.2257526270
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.852136096
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.1140283255
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.3012378625
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.1721482446
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.3165981547
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.3489245991
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.847871742
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.4262683311
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.3745943339
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.832028774
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.3594733486
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.4092995312
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.578493803
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.2816222688
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.1511286193
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3227557094
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2542418405
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.2950493701
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.1075577338
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.3961500813
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1406666410
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.1260794546
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.651117203
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.973262791
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.806548474
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.37986838
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.3230557228
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.781576245
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.1045649890
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.4194970307
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.3057559543
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.1977748511
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.4262250949
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2639238355
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.3600993591
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.1740532148
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.2918266061
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.3180184257
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.3954683234
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.180788229
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.3885190107
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.1040050354
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.3738989279
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.3781198831
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.1895748228
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2488620961
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.2501050118
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2614082232
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.4052189340
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.4098859662
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.273725133
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2474131816
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.2220470118
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.1929892633
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.3689048439
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.1117089278
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2332167273
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.2878614195
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.581988497



Total test records in report: 1150
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.3485102652 Sep 04 08:23:01 AM UTC 24 Sep 04 08:23:03 AM UTC 24 31034511 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.3505066791 Sep 04 08:23:02 AM UTC 24 Sep 04 08:23:05 AM UTC 24 42054905 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.4213243256 Sep 04 08:23:02 AM UTC 24 Sep 04 08:23:05 AM UTC 24 236848613 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.1768591555 Sep 04 08:23:06 AM UTC 24 Sep 04 08:23:08 AM UTC 24 24679873 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.3008163811 Sep 04 08:23:06 AM UTC 24 Sep 04 08:23:09 AM UTC 24 142970876 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.3295601724 Sep 04 08:23:06 AM UTC 24 Sep 04 08:23:11 AM UTC 24 102588820 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.900575929 Sep 04 08:23:08 AM UTC 24 Sep 04 08:23:13 AM UTC 24 370064424 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.521921274 Sep 04 08:23:09 AM UTC 24 Sep 04 08:23:14 AM UTC 24 281126457 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.1002131028 Sep 04 08:23:04 AM UTC 24 Sep 04 08:23:15 AM UTC 24 9662980066 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.3383737834 Sep 04 08:23:17 AM UTC 24 Sep 04 08:23:19 AM UTC 24 372535692 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3041449594 Sep 04 08:23:13 AM UTC 24 Sep 04 08:23:20 AM UTC 24 452312140 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.3902241462 Sep 04 08:23:20 AM UTC 24 Sep 04 08:23:22 AM UTC 24 15337917 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.3920094789 Sep 04 08:23:20 AM UTC 24 Sep 04 08:23:22 AM UTC 24 25012726 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.3905211713 Sep 04 08:23:20 AM UTC 24 Sep 04 08:23:23 AM UTC 24 124057146 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.2854373853 Sep 04 08:23:23 AM UTC 24 Sep 04 08:23:25 AM UTC 24 47225120 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.2261296798 Sep 04 08:23:23 AM UTC 24 Sep 04 08:23:26 AM UTC 24 224653917 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.1283179804 Sep 04 08:23:10 AM UTC 24 Sep 04 08:23:27 AM UTC 24 2765617044 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.434829788 Sep 04 08:23:04 AM UTC 24 Sep 04 08:23:28 AM UTC 24 5964976891 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2585973903 Sep 04 08:23:07 AM UTC 24 Sep 04 08:23:29 AM UTC 24 6015759551 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.3340253750 Sep 04 08:23:11 AM UTC 24 Sep 04 08:23:29 AM UTC 24 2649727420 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.3998004773 Sep 04 08:23:21 AM UTC 24 Sep 04 08:23:29 AM UTC 24 771472983 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3830652505 Sep 04 08:23:10 AM UTC 24 Sep 04 08:23:29 AM UTC 24 2231206126 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.3106769963 Sep 04 08:23:28 AM UTC 24 Sep 04 08:23:32 AM UTC 24 118054003 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.3891022778 Sep 04 08:23:23 AM UTC 24 Sep 04 08:23:33 AM UTC 24 2141954406 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.363424290 Sep 04 08:23:27 AM UTC 24 Sep 04 08:23:36 AM UTC 24 2495536188 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1659047971 Sep 04 08:23:30 AM UTC 24 Sep 04 08:23:36 AM UTC 24 194945992 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.1049284763 Sep 04 08:23:38 AM UTC 24 Sep 04 08:23:40 AM UTC 24 128651523 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.2229900959 Sep 04 08:23:12 AM UTC 24 Sep 04 08:23:42 AM UTC 24 16837497249 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.2475689485 Sep 04 08:23:41 AM UTC 24 Sep 04 08:23:43 AM UTC 24 13419215 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.1218948135 Sep 04 08:23:43 AM UTC 24 Sep 04 08:23:45 AM UTC 24 55820753 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.371657099 Sep 04 08:23:44 AM UTC 24 Sep 04 08:23:46 AM UTC 24 26230815 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.1445724543 Sep 04 08:23:32 AM UTC 24 Sep 04 08:23:47 AM UTC 24 1562114110 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.1725142567 Sep 04 08:23:26 AM UTC 24 Sep 04 08:23:47 AM UTC 24 13337467037 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.878920937 Sep 04 08:23:15 AM UTC 24 Sep 04 08:23:49 AM UTC 24 12647526664 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.2818347599 Sep 04 08:23:47 AM UTC 24 Sep 04 08:23:49 AM UTC 24 151386117 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.2100645399 Sep 04 08:23:48 AM UTC 24 Sep 04 08:23:51 AM UTC 24 156592317 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.1739803730 Sep 04 08:23:46 AM UTC 24 Sep 04 08:23:53 AM UTC 24 1301113602 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.1245615084 Sep 04 08:23:30 AM UTC 24 Sep 04 08:23:53 AM UTC 24 3417065523 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.1054844158 Sep 04 08:23:30 AM UTC 24 Sep 04 08:23:55 AM UTC 24 8286291239 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.3595772115 Sep 04 08:23:49 AM UTC 24 Sep 04 08:23:56 AM UTC 24 2508316763 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.4057659706 Sep 04 08:23:50 AM UTC 24 Sep 04 08:23:57 AM UTC 24 499245624 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.2924695032 Sep 04 08:23:32 AM UTC 24 Sep 04 08:24:04 AM UTC 24 5863617020 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.257375700 Sep 04 08:23:54 AM UTC 24 Sep 04 08:24:05 AM UTC 24 1472296888 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.668904636 Sep 04 08:23:58 AM UTC 24 Sep 04 08:24:06 AM UTC 24 823175865 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.3640094670 Sep 04 08:23:47 AM UTC 24 Sep 04 08:24:06 AM UTC 24 6563479913 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.2687004273 Sep 04 08:23:56 AM UTC 24 Sep 04 08:24:08 AM UTC 24 654574083 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.1514097161 Sep 04 08:24:06 AM UTC 24 Sep 04 08:24:09 AM UTC 24 205001466 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.4256604665 Sep 04 08:24:06 AM UTC 24 Sep 04 08:24:09 AM UTC 24 41971413 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.1305173008 Sep 04 08:23:51 AM UTC 24 Sep 04 08:24:09 AM UTC 24 6457469443 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.1565032811 Sep 04 08:24:08 AM UTC 24 Sep 04 08:24:10 AM UTC 24 19583994 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.3741711896 Sep 04 08:24:09 AM UTC 24 Sep 04 08:24:11 AM UTC 24 40907737 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.382004964 Sep 04 08:24:09 AM UTC 24 Sep 04 08:24:11 AM UTC 24 24635374 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.2742219758 Sep 04 08:24:10 AM UTC 24 Sep 04 08:24:12 AM UTC 24 87924146 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.2986653111 Sep 04 08:24:10 AM UTC 24 Sep 04 08:24:15 AM UTC 24 806891168 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.2121832544 Sep 04 08:24:15 AM UTC 24 Sep 04 08:24:19 AM UTC 24 111719000 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.480960348 Sep 04 08:24:12 AM UTC 24 Sep 04 08:24:21 AM UTC 24 646282564 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.826029823 Sep 04 08:24:10 AM UTC 24 Sep 04 08:24:24 AM UTC 24 3767931781 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.2490244324 Sep 04 08:24:12 AM UTC 24 Sep 04 08:24:25 AM UTC 24 16071715427 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.1836369587 Sep 04 08:24:10 AM UTC 24 Sep 04 08:24:28 AM UTC 24 1578213609 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.3281335477 Sep 04 08:24:13 AM UTC 24 Sep 04 08:24:29 AM UTC 24 3874237381 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.2429779389 Sep 04 08:23:29 AM UTC 24 Sep 04 08:24:30 AM UTC 24 5844939867 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.3442287659 Sep 04 08:24:21 AM UTC 24 Sep 04 08:24:30 AM UTC 24 338392096 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1247618222 Sep 04 08:24:17 AM UTC 24 Sep 04 08:24:31 AM UTC 24 929734573 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.3673345767 Sep 04 08:24:18 AM UTC 24 Sep 04 08:24:31 AM UTC 24 484322138 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.607925543 Sep 04 08:24:31 AM UTC 24 Sep 04 08:24:34 AM UTC 24 124493407 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.3807934162 Sep 04 08:24:32 AM UTC 24 Sep 04 08:24:34 AM UTC 24 227423107 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.863600643 Sep 04 08:24:32 AM UTC 24 Sep 04 08:24:34 AM UTC 24 41430640 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.2406892079 Sep 04 08:24:32 AM UTC 24 Sep 04 08:24:34 AM UTC 24 36564093 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.4118323164 Sep 04 08:24:35 AM UTC 24 Sep 04 08:24:38 AM UTC 24 33228676 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3461777384 Sep 04 08:24:35 AM UTC 24 Sep 04 08:24:38 AM UTC 24 141861229 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.1787603284 Sep 04 08:24:32 AM UTC 24 Sep 04 08:24:41 AM UTC 24 1936540597 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.706626612 Sep 04 08:23:14 AM UTC 24 Sep 04 08:24:44 AM UTC 24 17651375506 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.2120616901 Sep 04 08:24:16 AM UTC 24 Sep 04 08:24:45 AM UTC 24 5420341497 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.2554322161 Sep 04 08:24:35 AM UTC 24 Sep 04 08:24:46 AM UTC 24 2173974064 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.1682548322 Sep 04 08:24:37 AM UTC 24 Sep 04 08:24:49 AM UTC 24 6598845743 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.1688321849 Sep 04 08:24:42 AM UTC 24 Sep 04 08:24:49 AM UTC 24 924159527 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.1769818207 Sep 04 08:24:35 AM UTC 24 Sep 04 08:24:49 AM UTC 24 8857924616 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.834991158 Sep 04 08:24:40 AM UTC 24 Sep 04 08:24:50 AM UTC 24 876761566 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.1896785355 Sep 04 08:24:39 AM UTC 24 Sep 04 08:24:51 AM UTC 24 1076541462 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.4217718471 Sep 04 08:24:46 AM UTC 24 Sep 04 08:24:52 AM UTC 24 245372844 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.3528224882 Sep 04 08:24:50 AM UTC 24 Sep 04 08:24:52 AM UTC 24 176073711 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.1545428845 Sep 04 08:24:51 AM UTC 24 Sep 04 08:24:53 AM UTC 24 50803176 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.3574431945 Sep 04 08:24:52 AM UTC 24 Sep 04 08:24:54 AM UTC 24 93303411 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.2841279958 Sep 04 08:24:53 AM UTC 24 Sep 04 08:24:55 AM UTC 24 48976538 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2521432417 Sep 04 08:24:04 AM UTC 24 Sep 04 08:24:57 AM UTC 24 2254761407 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2402943001 Sep 04 08:24:55 AM UTC 24 Sep 04 08:24:57 AM UTC 24 22572318 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.1913283270 Sep 04 08:24:56 AM UTC 24 Sep 04 08:24:59 AM UTC 24 60178866 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.3394948727 Sep 04 08:24:59 AM UTC 24 Sep 04 08:25:05 AM UTC 24 86451336 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.45805882 Sep 04 08:24:25 AM UTC 24 Sep 04 08:25:05 AM UTC 24 4711042227 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2793305421 Sep 04 08:24:53 AM UTC 24 Sep 04 08:25:08 AM UTC 24 4473583123 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2315823571 Sep 04 08:25:05 AM UTC 24 Sep 04 08:25:09 AM UTC 24 368425989 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.2901092594 Sep 04 08:23:54 AM UTC 24 Sep 04 08:25:11 AM UTC 24 64161622546 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.2701326400 Sep 04 08:25:04 AM UTC 24 Sep 04 08:25:14 AM UTC 24 2452324173 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.970576576 Sep 04 08:24:59 AM UTC 24 Sep 04 08:25:16 AM UTC 24 1194263881 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.479296940 Sep 04 08:23:57 AM UTC 24 Sep 04 08:25:19 AM UTC 24 30578720369 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.3726083866 Sep 04 08:25:18 AM UTC 24 Sep 04 08:25:20 AM UTC 24 32137837 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.3729795127 Sep 04 08:24:58 AM UTC 24 Sep 04 08:25:20 AM UTC 24 7819986467 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.957651967 Sep 04 08:24:54 AM UTC 24 Sep 04 08:25:20 AM UTC 24 15854522210 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.3637672027 Sep 04 08:25:19 AM UTC 24 Sep 04 08:25:21 AM UTC 24 44178286 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1315152119 Sep 04 08:24:47 AM UTC 24 Sep 04 08:25:22 AM UTC 24 5559315060 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.2064791387 Sep 04 08:25:20 AM UTC 24 Sep 04 08:25:23 AM UTC 24 44383588 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.1721482446 Sep 04 08:25:21 AM UTC 24 Sep 04 08:25:23 AM UTC 24 87113615 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.1685145525 Sep 04 08:23:53 AM UTC 24 Sep 04 08:25:26 AM UTC 24 6561974559 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.3656280550 Sep 04 08:23:15 AM UTC 24 Sep 04 08:25:26 AM UTC 24 7539132104 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.3012378625 Sep 04 08:25:22 AM UTC 24 Sep 04 08:25:26 AM UTC 24 1826439765 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.1140283255 Sep 04 08:25:21 AM UTC 24 Sep 04 08:25:29 AM UTC 24 4695862466 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2869532075 Sep 04 08:25:22 AM UTC 24 Sep 04 08:25:31 AM UTC 24 3980223787 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.1703573371 Sep 04 08:25:10 AM UTC 24 Sep 04 08:25:31 AM UTC 24 2133959629 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.4218241639 Sep 04 08:25:24 AM UTC 24 Sep 04 08:25:31 AM UTC 24 240141087 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.852136096 Sep 04 08:25:21 AM UTC 24 Sep 04 08:25:33 AM UTC 24 2034602181 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.3165981547 Sep 04 08:25:27 AM UTC 24 Sep 04 08:25:34 AM UTC 24 479619136 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.2849471532 Sep 04 08:25:32 AM UTC 24 Sep 04 08:25:34 AM UTC 24 12365930 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.4262683311 Sep 04 08:25:32 AM UTC 24 Sep 04 08:25:34 AM UTC 24 158399436 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1619366282 Sep 04 08:25:27 AM UTC 24 Sep 04 08:25:34 AM UTC 24 452902129 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.1511286193 Sep 04 08:25:34 AM UTC 24 Sep 04 08:25:37 AM UTC 24 58906255 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.1260794546 Sep 04 08:25:35 AM UTC 24 Sep 04 08:25:38 AM UTC 24 13749040 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1406666410 Sep 04 08:25:35 AM UTC 24 Sep 04 08:25:38 AM UTC 24 22402804 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.651117203 Sep 04 08:25:35 AM UTC 24 Sep 04 08:25:38 AM UTC 24 150778843 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.2258255691 Sep 04 08:25:27 AM UTC 24 Sep 04 08:25:39 AM UTC 24 220622682 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.2269629868 Sep 04 08:25:06 AM UTC 24 Sep 04 08:25:40 AM UTC 24 3595305943 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.3961500813 Sep 04 08:25:35 AM UTC 24 Sep 04 08:25:40 AM UTC 24 303555531 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2332167273 Sep 04 08:26:06 AM UTC 24 Sep 04 08:26:10 AM UTC 24 759778581 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.2203783089 Sep 04 08:25:17 AM UTC 24 Sep 04 08:25:41 AM UTC 24 2399017937 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.3308403474 Sep 04 08:25:28 AM UTC 24 Sep 04 08:25:43 AM UTC 24 468396769 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.578493803 Sep 04 08:25:39 AM UTC 24 Sep 04 08:25:45 AM UTC 24 269988071 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2512560701 Sep 04 08:25:29 AM UTC 24 Sep 04 08:25:47 AM UTC 24 3069016579 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3227557094 Sep 04 08:25:38 AM UTC 24 Sep 04 08:25:47 AM UTC 24 551165610 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.1024960996 Sep 04 08:25:12 AM UTC 24 Sep 04 08:25:47 AM UTC 24 5535180927 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.2220733458 Sep 04 08:24:20 AM UTC 24 Sep 04 08:25:49 AM UTC 24 5303305133 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.3489245991 Sep 04 08:25:49 AM UTC 24 Sep 04 08:25:51 AM UTC 24 46886190 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.3230557228 Sep 04 08:25:49 AM UTC 24 Sep 04 08:25:51 AM UTC 24 19965779 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.1977748511 Sep 04 08:25:49 AM UTC 24 Sep 04 08:25:51 AM UTC 24 41922577 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.847871742 Sep 04 08:25:41 AM UTC 24 Sep 04 08:25:52 AM UTC 24 672407446 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.4091829590 Sep 04 08:24:44 AM UTC 24 Sep 04 08:25:54 AM UTC 24 14685308332 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.390751686 Sep 04 08:25:25 AM UTC 24 Sep 04 08:25:54 AM UTC 24 1790080694 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.3015197918 Sep 04 08:25:01 AM UTC 24 Sep 04 08:25:55 AM UTC 24 4919657608 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.180788229 Sep 04 08:25:52 AM UTC 24 Sep 04 08:25:55 AM UTC 24 41084740 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.3594733486 Sep 04 08:25:41 AM UTC 24 Sep 04 08:25:55 AM UTC 24 744179909 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.3954683234 Sep 04 08:25:52 AM UTC 24 Sep 04 08:25:55 AM UTC 24 112476782 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2542418405 Sep 04 08:25:37 AM UTC 24 Sep 04 08:25:57 AM UTC 24 3426340811 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2639238355 Sep 04 08:25:53 AM UTC 24 Sep 04 08:25:58 AM UTC 24 170233540 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.4194970307 Sep 04 08:25:54 AM UTC 24 Sep 04 08:25:59 AM UTC 24 183523725 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.3885190107 Sep 04 08:25:56 AM UTC 24 Sep 04 08:26:00 AM UTC 24 169460317 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.4262250949 Sep 04 08:25:54 AM UTC 24 Sep 04 08:26:00 AM UTC 24 345601884 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.2950493701 Sep 04 08:25:41 AM UTC 24 Sep 04 08:26:02 AM UTC 24 1761216102 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.2551457064 Sep 04 08:23:58 AM UTC 24 Sep 04 08:26:02 AM UTC 24 29869235432 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1400778363 Sep 04 08:25:22 AM UTC 24 Sep 04 08:26:03 AM UTC 24 104430891771 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1413427237 Sep 04 08:25:32 AM UTC 24 Sep 04 08:26:03 AM UTC 24 17635212586 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.3180184257 Sep 04 08:25:50 AM UTC 24 Sep 04 08:26:04 AM UTC 24 5927718360 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.3215344951 Sep 04 08:23:34 AM UTC 24 Sep 04 08:26:05 AM UTC 24 9842705379 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.37986838 Sep 04 08:25:56 AM UTC 24 Sep 04 08:26:05 AM UTC 24 440419018 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.806548474 Sep 04 08:26:03 AM UTC 24 Sep 04 08:26:05 AM UTC 24 56965712 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.3781198831 Sep 04 08:26:03 AM UTC 24 Sep 04 08:26:05 AM UTC 24 33061681 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.4098859662 Sep 04 08:26:03 AM UTC 24 Sep 04 08:26:06 AM UTC 24 83297071 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.2977659314 Sep 04 08:25:09 AM UTC 24 Sep 04 08:26:06 AM UTC 24 3611176810 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.2878614195 Sep 04 08:26:06 AM UTC 24 Sep 04 08:26:08 AM UTC 24 80161780 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.4092995312 Sep 04 08:25:41 AM UTC 24 Sep 04 08:26:12 AM UTC 24 3573394548 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.3600993591 Sep 04 08:25:59 AM UTC 24 Sep 04 08:26:13 AM UTC 24 3936352278 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.973262791 Sep 04 08:25:40 AM UTC 24 Sep 04 08:26:13 AM UTC 24 31777723318 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.1117089278 Sep 04 08:26:04 AM UTC 24 Sep 04 08:26:13 AM UTC 24 754219602 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.3738989279 Sep 04 08:26:11 AM UTC 24 Sep 04 08:26:16 AM UTC 24 414730863 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.2918266061 Sep 04 08:25:52 AM UTC 24 Sep 04 08:26:16 AM UTC 24 3407479827 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.581988497 Sep 04 08:26:09 AM UTC 24 Sep 04 08:26:17 AM UTC 24 1587532752 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.2501050118 Sep 04 08:26:13 AM UTC 24 Sep 04 08:26:17 AM UTC 24 38417422 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.1075577338 Sep 04 08:25:48 AM UTC 24 Sep 04 08:26:19 AM UTC 24 16658618975 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.3057559543 Sep 04 08:25:56 AM UTC 24 Sep 04 08:26:20 AM UTC 24 1396783159 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.1040050354 Sep 04 08:26:19 AM UTC 24 Sep 04 08:26:21 AM UTC 24 16819232 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.2220470118 Sep 04 08:26:14 AM UTC 24 Sep 04 08:26:21 AM UTC 24 225603415 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.2816222688 Sep 04 08:25:40 AM UTC 24 Sep 04 08:26:22 AM UTC 24 4164436239 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.3811342103 Sep 04 08:26:20 AM UTC 24 Sep 04 08:26:22 AM UTC 24 38990912 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.273725133 Sep 04 08:26:07 AM UTC 24 Sep 04 08:26:23 AM UTC 24 2472752806 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.3936649919 Sep 04 08:26:21 AM UTC 24 Sep 04 08:26:23 AM UTC 24 119578148 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.1030373807 Sep 04 08:25:15 AM UTC 24 Sep 04 08:26:24 AM UTC 24 32393075232 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.3630772899 Sep 04 08:24:39 AM UTC 24 Sep 04 08:26:24 AM UTC 24 24334393461 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1394996851 Sep 04 08:26:23 AM UTC 24 Sep 04 08:26:25 AM UTC 24 71821316 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.1045649890 Sep 04 08:25:57 AM UTC 24 Sep 04 08:26:25 AM UTC 24 1244543425 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.2911568556 Sep 04 08:26:23 AM UTC 24 Sep 04 08:26:25 AM UTC 24 30148875 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.1571142701 Sep 04 08:26:22 AM UTC 24 Sep 04 08:26:27 AM UTC 24 1028577864 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2474131816 Sep 04 08:26:06 AM UTC 24 Sep 04 08:26:28 AM UTC 24 8076388950 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2276542658 Sep 04 08:27:10 AM UTC 24 Sep 04 08:27:13 AM UTC 24 100707838 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.1111629069 Sep 04 08:26:24 AM UTC 24 Sep 04 08:26:30 AM UTC 24 126834430 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2488620961 Sep 04 08:26:17 AM UTC 24 Sep 04 08:26:30 AM UTC 24 5005410735 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.781576245 Sep 04 08:26:00 AM UTC 24 Sep 04 08:26:32 AM UTC 24 6967341221 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.1463062160 Sep 04 08:23:36 AM UTC 24 Sep 04 08:26:32 AM UTC 24 27549310069 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.4020607877 Sep 04 08:26:33 AM UTC 24 Sep 04 08:26:35 AM UTC 24 40470551 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.2711287558 Sep 04 08:26:27 AM UTC 24 Sep 04 08:26:35 AM UTC 24 764688678 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.3916747448 Sep 04 08:26:22 AM UTC 24 Sep 04 08:26:37 AM UTC 24 1257404769 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.1929892633 Sep 04 08:26:18 AM UTC 24 Sep 04 08:26:38 AM UTC 24 5515187484 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.2804765666 Sep 04 08:26:36 AM UTC 24 Sep 04 08:26:38 AM UTC 24 105321158 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.832028774 Sep 04 08:25:43 AM UTC 24 Sep 04 08:26:39 AM UTC 24 6930299273 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.2703378138 Sep 04 08:26:36 AM UTC 24 Sep 04 08:26:39 AM UTC 24 121454524 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1992945641 Sep 04 08:26:40 AM UTC 24 Sep 04 08:26:42 AM UTC 24 189072884 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.633443543 Sep 04 08:26:38 AM UTC 24 Sep 04 08:26:42 AM UTC 24 376876868 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.2117848545 Sep 04 08:26:25 AM UTC 24 Sep 04 08:26:43 AM UTC 24 6489743238 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.1293587524 Sep 04 08:26:40 AM UTC 24 Sep 04 08:26:43 AM UTC 24 49216282 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.1653467103 Sep 04 08:24:50 AM UTC 24 Sep 04 08:26:45 AM UTC 24 59392205225 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.1718106893 Sep 04 08:26:40 AM UTC 24 Sep 04 08:26:45 AM UTC 24 169222954 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.2672385824 Sep 04 08:26:30 AM UTC 24 Sep 04 08:26:46 AM UTC 24 20489150715 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.3734522714 Sep 04 08:26:24 AM UTC 24 Sep 04 08:26:46 AM UTC 24 23445002392 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.807675484 Sep 04 08:26:27 AM UTC 24 Sep 04 08:26:48 AM UTC 24 818417140 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.2479263605 Sep 04 08:26:24 AM UTC 24 Sep 04 08:26:48 AM UTC 24 64619620545 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.3689048439 Sep 04 08:26:06 AM UTC 24 Sep 04 08:26:48 AM UTC 24 3208956478 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.2890335600 Sep 04 08:26:43 AM UTC 24 Sep 04 08:26:50 AM UTC 24 159840698 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.2837058882 Sep 04 08:26:46 AM UTC 24 Sep 04 08:26:51 AM UTC 24 195642661 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.4268281252 Sep 04 08:26:45 AM UTC 24 Sep 04 08:26:51 AM UTC 24 191763723 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.1660429981 Sep 04 08:26:49 AM UTC 24 Sep 04 08:26:51 AM UTC 24 34992989 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.4052189340 Sep 04 08:26:07 AM UTC 24 Sep 04 08:26:51 AM UTC 24 11419559149 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.1164493706 Sep 04 08:26:51 AM UTC 24 Sep 04 08:26:53 AM UTC 24 45630917 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2614082232 Sep 04 08:26:07 AM UTC 24 Sep 04 08:26:54 AM UTC 24 21066891152 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.396934245 Sep 04 08:26:52 AM UTC 24 Sep 04 08:26:54 AM UTC 24 26297757 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.2797940765 Sep 04 08:26:52 AM UTC 24 Sep 04 08:26:54 AM UTC 24 15785512 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.3069333242 Sep 04 08:26:25 AM UTC 24 Sep 04 08:26:55 AM UTC 24 2845913149 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.945286151 Sep 04 08:26:01 AM UTC 24 Sep 04 08:26:55 AM UTC 24 62294716080 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.273627808 Sep 04 08:26:54 AM UTC 24 Sep 04 08:26:57 AM UTC 24 378253573 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.3279716177 Sep 04 08:26:52 AM UTC 24 Sep 04 08:26:57 AM UTC 24 1712669952 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.4148467960 Sep 04 08:26:40 AM UTC 24 Sep 04 08:26:58 AM UTC 24 1304411699 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.3778535978 Sep 04 08:26:47 AM UTC 24 Sep 04 08:26:58 AM UTC 24 2650279490 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.1293232488 Sep 04 08:26:55 AM UTC 24 Sep 04 08:26:58 AM UTC 24 28885387 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.2842650615 Sep 04 08:26:55 AM UTC 24 Sep 04 08:27:01 AM UTC 24 492657154 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.4077868276 Sep 04 08:24:28 AM UTC 24 Sep 04 08:27:03 AM UTC 24 105683583496 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.398021892 Sep 04 08:26:52 AM UTC 24 Sep 04 08:27:04 AM UTC 24 5643856364 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.319048138 Sep 04 08:26:58 AM UTC 24 Sep 04 08:27:04 AM UTC 24 433648949 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.4190850603 Sep 04 08:23:15 AM UTC 24 Sep 04 08:27:05 AM UTC 24 357015474548 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.143645910 Sep 04 08:26:58 AM UTC 24 Sep 04 08:27:07 AM UTC 24 202189333 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.1212835151 Sep 04 08:27:05 AM UTC 24 Sep 04 08:27:08 AM UTC 24 30780047 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.1261450171 Sep 04 08:26:57 AM UTC 24 Sep 04 08:27:08 AM UTC 24 1978897992 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.691719736 Sep 04 08:23:36 AM UTC 24 Sep 04 08:27:09 AM UTC 24 90514884105 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.779539904 Sep 04 08:27:07 AM UTC 24 Sep 04 08:27:09 AM UTC 24 46311559 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.2779950290 Sep 04 08:26:43 AM UTC 24 Sep 04 08:27:09 AM UTC 24 28790310834 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.2004840036 Sep 04 08:26:57 AM UTC 24 Sep 04 08:27:09 AM UTC 24 1423862706 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.280977364 Sep 04 08:27:09 AM UTC 24 Sep 04 08:27:11 AM UTC 24 51824579 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.2519933660 Sep 04 08:26:55 AM UTC 24 Sep 04 08:27:15 AM UTC 24 12257908082 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3381318148 Sep 04 08:26:55 AM UTC 24 Sep 04 08:27:12 AM UTC 24 1660561772 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.3252839130 Sep 04 08:27:10 AM UTC 24 Sep 04 08:27:12 AM UTC 24 19804985 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.238512296 Sep 04 08:23:31 AM UTC 24 Sep 04 08:27:16 AM UTC 24 24120178225 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1598521495 Sep 04 08:27:13 AM UTC 24 Sep 04 08:27:17 AM UTC 24 78427140 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.2626060227 Sep 04 08:27:13 AM UTC 24 Sep 04 08:27:17 AM UTC 24 40908089 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.455675136 Sep 04 08:27:12 AM UTC 24 Sep 04 08:27:18 AM UTC 24 135895573 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.3238538735 Sep 04 08:26:43 AM UTC 24 Sep 04 08:27:19 AM UTC 24 16311268124 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.688012146 Sep 04 08:26:59 AM UTC 24 Sep 04 08:27:22 AM UTC 24 1769592392 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.2770137497 Sep 04 08:26:46 AM UTC 24 Sep 04 08:27:24 AM UTC 24 1640299459 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.1835788727 Sep 04 08:27:10 AM UTC 24 Sep 04 08:27:26 AM UTC 24 1802166641 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.2946320275 Sep 04 08:26:43 AM UTC 24 Sep 04 08:27:26 AM UTC 24 21094791305 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.2036643113 Sep 04 08:27:25 AM UTC 24 Sep 04 08:27:28 AM UTC 24 16680141 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.3661789548 Sep 04 08:27:28 AM UTC 24 Sep 04 08:27:30 AM UTC 24 15138442 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.3388767572 Sep 04 08:27:18 AM UTC 24 Sep 04 08:27:30 AM UTC 24 1168735994 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.460498632 Sep 04 08:27:28 AM UTC 24 Sep 04 08:27:31 AM UTC 24 85244170 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.3225079034 Sep 04 08:26:28 AM UTC 24 Sep 04 08:27:31 AM UTC 24 4301086082 ps
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T484 /workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.402062384 Sep 04 08:27:31 AM UTC 24 Sep 04 08:27:34 AM UTC 24 243653305 ps
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