Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35005	1			T6	2		T15	195		T16	6
auto[SpiFlashAddrCfg]	7436	1			T7	2		T8	2		T15	6
auto[SpiFlashAddr3b]	8780	1			T16	8		T43	1		T40	4
auto[SpiFlashAddr4b]	7326	1			T8	2		T15	6		T16	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33072

1

T6

2

T7

2

T8

4

auto[1]

25475

1

T16

20

T19

10

T43

11

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30069

1

T8

2

T15

197

T16

2

auto[1]

28478

1

T6

2

T7

2

T8

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39448	1			T6	2		T15	199		T16	10
values[1]	1115	1			T15	4		T40	2		T74	3
values[2]	1388	1			T15	4		T16	2		T17	1
values[3]	1485	1			T8	2		T19	4		T44	2
values[4]	1411	1			T7	2		T44	2		T170	1
values[5]	1453	1			T16	2		T43	1		T55	2
values[6]	1484	1			T16	2		T48	1		T170	1
values[7]	1434	1			T74	6		T59	2		T56	2
values[8]	9329	1			T8	2		T16	4		T43	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30014

1

T6

2

T7

2

T8

4

auto[1]

28533

1

T17

1

T43

20

T44

61

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55375

1

T6

2

T7

2

T8

4

write

3172

1

T15

8

T16

4

T43

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18488

1

T7

2

T8

2

T16

4

valids[0x1]

40059

1

T6

2

T8

2

T15

207

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1556	1			T43	2		T44	2		T55	2
internal_process_ops[0x5a]	1546	1			T16	2		T43	1		T44	1
internal_process_ops[0x05]	21626	1			T15	191		T16	6		T19	2
internal_process_ops[0x35]	1524	1			T43	1		T52	2		T53	2
internal_process_ops[0x15]	1446	1			T43	1		T52	2		T192	8
internal_process_ops[0x03]	1053	1			T8	2		T15	4		T16	2
internal_process_ops[0x0b]	1043	1			T40	2		T45	3		T48	3
internal_process_ops[0x3b]	1011	1			T16	2		T17	1		T45	1
internal_process_ops[0x6b]	1001	1			T40	2		T46	2		T95	2
internal_process_ops[0xbb]	991	1			T7	2		T8	2		T45	2
internal_process_ops[0xeb]	1020	1			T45	2		T46	2		T115	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56961

1

T6

2

T7

2

T8

4

auto[1]

1586

1

T16

4

T43

1

T44

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56244

1

T6

2

T7

2

T8

4

auto[1]

2303

1

T15

6

T43

2

T44

5

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9953

1

T6

2

T15

195

T18

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6588

1

T16

6

T19

2

T57

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1992

1

T7

2

T8

2

T15

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1790

1

T16

4

T19

4

T57

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2324

1

T40

4

T52

8

T46

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2109

1

T16

4

T55

2

T51

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1977

1

T8

2

T46

2

T115

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1702

1

T16

2

T19

4

T55

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

118

1

T59

4

T56

2

T60

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

90

1

T58

1

T193

1

T194

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

89

1

T61

1

T58

1

T118

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

91

1

T60

1

T58

1

T67

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

154

1

T15

2

T195

2

T196

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

65

1

T60

1

T58

6

T197

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

82

1

T58

3

T65

3

T67

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

95

1

T62

1

T65

1

T67

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

102

1

T59

6

T60

2

T61

7

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

95

1

T51

1

T58

2

T191

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

92

1

T34

3

T61

1

T65

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

104

1

T16

4

T51

1

T58

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

122

1

T15

6

T40

4

T51

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

90

1

T58

2

T197

1

T198

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

92

1

T61

1

T58

2

T118

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

98

1

T62

1

T63

4

T64

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10517

1

T43

5

T44

3

T48

60

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7149

1

T43

5

T44

42

T48

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1464

1

T17

1

T44

5

T45

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1403

1

T43

2

T44

2

T74

10

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1736

1

T43

1

T44

1

T45

4

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1809

1

T44

2

T48

4

T74

7

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1453

1

T43

2

T44

1

T45

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1409

1

T43

3

T74

3

T73

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

94

1

T92

1

T93

1

T102

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

100

1

T102

1

T199

2

T36

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

105

1

T44

1

T48

2

T93

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

111

1

T92

2

T93

2

T102

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

102

1

T92

1

T200

1

T180

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

107

1

T44

1

T92

1

T102

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

79

1

T43

1

T48

1

T93

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

103

1

T44

3

T74

3

T93

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

102

1

T92

1

T102

4

T200

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

120

1

T92

3

T93

1

T102

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

72

1

T92

1

T201

1

T36

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

115

1

T73

2

T93

4

T102

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

82

1

T93

8

T199

1

T37

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

113

1

T43

1

T74

1

T93

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

99

1

T74

1

T73

2

T201

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

89

1

T35

1

T36

3

T37

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3662	1			T18	6		T20	14		T52	2
auto[0]	values[0]	valids[0x1]	15601	1			T6	2		T15	199		T16	10
auto[0]	values[1]	valids[0x1]	599	1			T15	4		T40	2		T51	4
auto[0]	values[2]	valids[0x0]	537	1			T16	2		T40	2		T52	2
auto[0]	values[2]	valids[0x1]	260	1			T15	4		T57	2		T51	3
auto[0]	values[3]	valids[0x0]	538	1			T8	2		T52	2		T56	2
auto[0]	values[3]	valids[0x1]	343	1			T19	4		T50	2		T117	4
auto[0]	values[4]	valids[0x0]	515	1			T7	2		T115	2		T51	2
auto[0]	values[4]	valids[0x1]	324	1			T51	1		T61	5		T58	2
auto[0]	values[5]	valids[0x0]	491	1			T55	2		T54	2		T51	3
auto[0]	values[5]	valids[0x1]	307	1			T16	2		T195	4		T34	1
auto[0]	values[6]	valids[0x0]	589	1			T16	2		T55	2		T196	2
auto[0]	values[6]	valids[0x1]	301	1			T54	2		T196	4		T60	3
auto[0]	values[7]	valids[0x0]	486	1			T59	2		T56	2		T51	2
auto[0]	values[7]	valids[0x1]	287	1			T50	6		T51	3		T61	2
auto[0]	values[8]	valids[0x0]	3273	1			T40	6		T46	4		T115	4
auto[0]	values[8]	valids[0x1]	1901	1			T8	2		T16	4		T40	4
auto[1]	values[0]	valids[0x0]	3735	1			T43	7		T44	1		T48	4
auto[1]	values[0]	valids[0x1]	16450	1			T43	8		T44	50		T45	3
auto[1]	values[1]	valids[0x1]	516	1			T74	3		T73	1		T93	8
auto[1]	values[2]	valids[0x0]	364	1			T17	1		T74	2		T92	5
auto[1]	values[2]	valids[0x1]	227	1			T74	1		T93	5		T102	4
auto[1]	values[3]	valids[0x0]	365	1			T92	4		T93	7		T102	3
auto[1]	values[3]	valids[0x1]	239	1			T44	2		T73	1		T93	7
auto[1]	values[4]	valids[0x0]	344	1			T44	2		T170	1		T92	4
auto[1]	values[4]	valids[0x1]	228	1			T92	3		T93	4		T102	1
auto[1]	values[5]	valids[0x0]	390	1			T74	1		T92	1		T93	7
auto[1]	values[5]	valids[0x1]	265	1			T43	1		T73	4		T93	2
auto[1]	values[6]	valids[0x0]	362	1			T48	1		T74	4		T73	2
auto[1]	values[6]	valids[0x1]	232	1			T170	1		T49	1		T73	2
auto[1]	values[7]	valids[0x0]	393	1			T74	2		T92	4		T93	6
auto[1]	values[7]	valids[0x1]	268	1			T74	4		T73	6		T93	1
auto[1]	values[8]	valids[0x0]	2444	1			T43	2		T44	5		T45	5
auto[1]	values[8]	valids[0x1]	1711	1			T43	2		T44	1		T48	3