Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3220804

1

T6

1

T7

36

T8

310

auto[1]

29984

1

T15

191

T43

29

T44

41

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

949764

1

T6

1

T7

36

T8

310

auto[1]

2301024

1

T15

191

T43

261

T44

41

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	578338	1			T6	1		T7	14		T8	198
auto[524288:1048575]	427054	1			T17	1770		T18	1870		T20	3
auto[1048576:1572863]	352781	1			T20	6		T43	2		T44	5
auto[1572864:2097151]	368321	1			T44	2		T45	158		T46	2128
auto[2097152:2621439]	398407	1			T7	12		T8	112		T20	50
auto[2621440:3145727]	411446	1			T18	565		T20	50		T43	264
auto[3145728:3670015]	333374	1			T17	6		T18	588		T20	236
auto[3670016:4194303]	381067	1			T7	10		T18	1858		T20	119

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2333063

1

T6

1

T7

8

T8

9

auto[1]

917725

1

T7

28

T8

301

T15

3

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2826476

1

T6

1

T7

36

T8

310

auto[1]

424312

1

T43

10

T74

769

T73

2357

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	207641	1			T6	1		T7	14		T8	198
auto[0]	auto[0]	auto[0:524287]	auto[1]	298298	1			T15	6		T44	3		T52	1042
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	138954	1			T17	1770		T18	1870		T20	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	230069	1			T46	1		T192	4		T74	768
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	85382	1			T20	6		T43	2		T44	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	230135	1			T44	1		T48	2		T74	2319
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	114021	1			T44	2		T45	158		T46	2127
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	198975	1			T46	1		T192	1		T74	3373
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	77039	1			T7	12		T8	112		T20	50
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	264852	1			T192	8		T92	1		T93	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	119234	1			T18	565		T20	50		T43	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	227251	1			T43	233		T44	1		T48	256
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	105027	1			T17	6		T18	588		T20	236
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	189982	1			T43	5		T73	374		T92	389
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	89135	1			T7	10		T18	1858		T20	119
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	225340	1			T48	512		T192	2714		T74	642
auto[0]	auto[1]	auto[0:524287]	auto[0]	1210	1			T92	3		T93	4		T102	21
auto[0]	auto[1]	auto[0:524287]	auto[1]	66564	1			T73	1024		T93	256		T61	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2752	1			T93	3		T102	5		T247	32
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	51683	1			T93	1		T247	1436		T36	5
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1221	1			T74	1		T92	2		T93	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	30743	1			T74	512		T51	5		T247	7
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	604	1			T92	14		T93	1		T60	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	51163	1			T92	4		T61	514		T58	1575
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1946	1			T92	33		T93	5		T60	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	50970	1			T92	919		T93	884		T60	5757
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	941	1			T73	5		T51	2		T92	30
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	59994	1			T73	209		T51	512		T92	516
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	481	1			T43	10		T73	9		T92	11
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	35027	1			T73	1097		T93	1		T201	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	591	1			T73	1		T92	4		T34	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	63579	1			T74	256		T92	5		T34	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	529	1			T15	6		T43	3		T44	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	3352	1			T15	185		T44	11		T59	90
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	392	1			T93	7		T102	16		T36	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2589	1			T93	62		T36	10		T180	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	341	1			T44	1		T48	2		T92	9
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	4611	1			T44	1		T48	54		T93	39
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	310	1			T74	1		T93	3		T102	13
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2553	1			T74	10		T93	55		T61	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	373	1			T93	1		T60	4		T102	9
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2507	1			T60	47		T61	6		T58	79
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	355	1			T43	3		T44	1		T92	9
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2911	1			T43	23		T44	24		T93	6
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	321	1			T92	6		T93	1		T102	25
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2054	1			T93	3		T102	84		T61	10
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	336	1			T74	2		T51	1		T92	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1607	1			T74	3		T93	7		T34	10
auto[1]	auto[1]	auto[0:524287]	auto[0]	122	1			T92	3		T102	8		T61	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	622	1			T61	5		T180	2		T291	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	61	1			T93	1		T37	1		T236	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	554	1			T37	3		T236	1		T233	40
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	71	1			T36	1		T180	1		T118	6
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	277	1			T36	3		T180	2		T261	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	92	1			T61	2		T247	3		T243	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	603	1			T61	26		T243	3		T211	38
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	79	1			T92	3		T93	1		T60	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	641	1			T93	3		T60	45		T58	60
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	77	1			T73	1		T92	12		T58	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	683	1			T73	2		T58	10		T249	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	71	1			T73	2		T93	1		T291	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	411	1			T73	7		T93	18		T283	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	55	1			T34	1		T181	1		T118	5
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	424	1			T34	15		T181	1		T292	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1889745	1			T6	1		T7	8		T8	9
auto[0]	auto[0]	auto[1]	911590	1			T7	28		T8	301		T15	2
auto[0]	auto[1]	auto[0]	413944	1			T43	10		T74	769		T73	2345
auto[0]	auto[1]	auto[1]	5525	1			T93	1		T61	1		T58	1
auto[1]	auto[0]	auto[0]	24641	1			T15	190		T43	27		T44	36
auto[1]	auto[0]	auto[1]	500	1			T15	1		T43	2		T44	5
auto[1]	auto[1]	auto[0]	4733	1			T73	12		T92	14		T93	24
auto[1]	auto[1]	auto[1]	110	1			T92	4		T60	1		T102	1