Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2544404	1			T1	1		T2	1		T4	1
all_pins[1]	2544404	1			T1	1		T2	1		T4	1
all_pins[2]	2544404	1			T1	1		T2	1		T4	1
all_pins[3]	2544404	1			T1	1		T2	1		T4	1
all_pins[4]	2544404	1			T1	1		T2	1		T4	1
all_pins[5]	2544404	1			T1	1		T2	1		T4	1
all_pins[6]	2544404	1			T1	1		T2	1		T4	1
all_pins[7]	2544404	1			T1	1		T2	1		T4	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20246110	1			T1	8		T2	8		T4	8
values[0x1]	109122	1			T22	18		T34	1546		T35	18
transitions[0x0=>0x1]	108413	1			T22	14		T34	1379		T35	13
transitions[0x1=>0x0]	108435	1			T22	14		T34	1380		T35	13

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2543392	1			T1	1		T2	1		T4	1
all_pins[0]	values[0x1]	1012	1			T22	4		T34	6		T180	72
all_pins[0]	transitions[0x0=>0x1]	886	1			T22	4		T34	4		T180	47
all_pins[0]	transitions[0x1=>0x0]	179	1			T34	36		T35	1		T37	2
all_pins[1]	values[0x0]	2544099	1			T1	1		T2	1		T4	1
all_pins[1]	values[0x1]	305	1			T34	38		T35	1		T37	2
all_pins[1]	transitions[0x0=>0x1]	243	1			T34	27		T35	1		T37	2
all_pins[1]	transitions[0x1=>0x0]	330	1			T22	4		T34	7		T37	2
all_pins[2]	values[0x0]	2544012	1			T1	1		T2	1		T4	1
all_pins[2]	values[0x1]	392	1			T22	4		T34	18		T37	2
all_pins[2]	transitions[0x0=>0x1]	335	1			T22	4		T34	16		T180	4
all_pins[2]	transitions[0x1=>0x0]	154	1			T22	1		T34	1		T35	4
all_pins[3]	values[0x0]	2544193	1			T1	1		T2	1		T4	1
all_pins[3]	values[0x1]	211	1			T22	1		T34	3		T35	4
all_pins[3]	transitions[0x0=>0x1]	171	1			T22	1		T34	3		T35	1
all_pins[3]	transitions[0x1=>0x0]	153	1			T22	1		T34	2		T37	3
all_pins[4]	values[0x0]	2544211	1			T1	1		T2	1		T4	1
all_pins[4]	values[0x1]	193	1			T22	1		T34	2		T35	3
all_pins[4]	transitions[0x0=>0x1]	150	1			T22	1		T34	1		T35	2
all_pins[4]	transitions[0x1=>0x0]	1918	1			T22	2		T34	151		T35	3
all_pins[5]	values[0x0]	2542443	1			T1	1		T2	1		T4	1
all_pins[5]	values[0x1]	1961	1			T22	2		T34	152		T35	4
all_pins[5]	transitions[0x0=>0x1]	1703	1			T22	1		T34	6		T35	3
all_pins[5]	transitions[0x1=>0x0]	104591	1			T22	2		T34	1173		T35	1
all_pins[6]	values[0x0]	2439555	1			T1	1		T2	1		T4	1
all_pins[6]	values[0x1]	104849	1			T22	3		T34	1319		T35	2
all_pins[6]	transitions[0x0=>0x1]	104798	1			T22	1		T34	1317		T35	2
all_pins[6]	transitions[0x1=>0x0]	148	1			T22	1		T34	6		T35	4
all_pins[7]	values[0x0]	2544205	1			T1	1		T2	1		T4	1
all_pins[7]	values[0x1]	199	1			T22	3		T34	8		T35	4
all_pins[7]	transitions[0x0=>0x1]	127	1			T22	2		T34	5		T35	4
all_pins[7]	transitions[0x1=>0x0]	962	1			T22	3		T34	4		T180	72