Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17082

1

T6

2

T7

2

T8

4

auto[1]

12932

1

T16

20

T19

10

T57

4

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2961	1			T6	2		T19	10		T20	14
values[1]	3629	1			T40	20		T51	21		T213	8
values[2]	4119	1			T95	2		T56	14		T114	2
values[3]	4270	1			T18	6		T53	6		T57	4
values[4]	3917	1			T15	207		T116	4		T61	20
values[5]	3730	1			T8	4		T52	16		T50	20
values[6]	3709	1			T7	2		T293	4		T294	6
values[7]	3679	1			T16	20		T55	14		T51	44

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3369	1			T16	20		T20	14		T96	2
values[1]	3779	1			T6	2		T57	4		T115	16
values[2]	3814	1			T52	16		T95	2		T192	8
values[3]	3802	1			T40	20		T46	6		T114	2
values[4]	4455	1			T7	2		T15	207		T51	21
values[5]	3821	1			T53	6		T293	4		T110	10
values[6]	3686	1			T18	6		T56	14		T51	24
values[7]	3288	1			T8	4		T19	10		T34	39

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	201	1			T20	14		T58	16		T65	11
auto[0]	values[0]	values[1]	179	1			T6	2		T115	16		T253	20
auto[0]	values[0]	values[2]	212	1			T192	8		T191	6		T233	23
auto[0]	values[0]	values[3]	277	1			T60	13		T191	13		T295	10
auto[0]	values[0]	values[4]	211	1			T227	14		T296	2		T224	93
auto[0]	values[0]	values[5]	259	1			T287	14		T225	24		T67	20
auto[0]	values[0]	values[6]	170	1			T297	2		T60	10		T65	14
auto[0]	values[0]	values[7]	258	1			T298	2		T299	4		T67	10
auto[0]	values[1]	values[0]	257	1			T300	2		T233	42		T301	10
auto[0]	values[1]	values[1]	180	1			T278	20		T224	13		T302	22
auto[0]	values[1]	values[2]	419	1			T252	15		T233	13		T155	6
auto[0]	values[1]	values[3]	166	1			T40	20		T303	4		T191	14
auto[0]	values[1]	values[4]	219	1			T51	11		T118	19		T224	12
auto[0]	values[1]	values[5]	299	1			T110	10		T68	11		T304	12
auto[0]	values[1]	values[6]	177	1			T213	8		T221	4		T231	10
auto[0]	values[1]	values[7]	263	1			T218	16		T62	13		T305	11
auto[0]	values[2]	values[0]	160	1			T306	4		T224	10		T307	12
auto[0]	values[2]	values[1]	373	1			T272	2		T247	13		T257	8
auto[0]	values[2]	values[2]	260	1			T95	2		T61	12		T65	11
auto[0]	values[2]	values[3]	373	1			T114	2		T34	12		T61	27
auto[0]	values[2]	values[4]	200	1			T308	2		T222	2		T309	2
auto[0]	values[2]	values[5]	347	1			T194	14		T255	10		T220	13
auto[0]	values[2]	values[6]	308	1			T56	14		T212	10		T60	18
auto[0]	values[2]	values[7]	180	1			T58	14		T310	6		T233	16
auto[0]	values[3]	values[0]	268	1			T96	2		T101	36		T68	13
auto[0]	values[3]	values[1]	339	1			T59	116		T68	8		T230	8
auto[0]	values[3]	values[2]	315	1			T58	11		T197	4		T235	113
auto[0]	values[3]	values[3]	294	1			T46	6		T288	6		T229	12
auto[0]	values[3]	values[4]	329	1			T311	8		T194	15		T235	182
auto[0]	values[3]	values[5]	180	1			T53	6		T312	2		T313	17
auto[0]	values[3]	values[6]	312	1			T18	6		T247	13		T68	12
auto[0]	values[3]	values[7]	285	1			T34	32		T314	22		T194	14
auto[0]	values[4]	values[0]	252	1			T279	18		T235	11		T230	7
auto[0]	values[4]	values[1]	267	1			T61	14		T315	4		T224	8
auto[0]	values[4]	values[2]	351	1			T316	102		T65	11		T68	12
auto[0]	values[4]	values[3]	270	1			T118	8		T224	63		T235	8
auto[0]	values[4]	values[4]	554	1			T15	207		T317	2		T233	71
auto[0]	values[4]	values[5]	242	1			T318	8		T65	12		T68	8
auto[0]	values[4]	values[6]	201	1			T194	14		T230	13		T319	4
auto[0]	values[4]	values[7]	184	1			T233	15		T301	10		T320	12
auto[0]	values[5]	values[0]	163	1			T60	34		T68	10		T267	6
auto[0]	values[5]	values[1]	199	1			T50	20		T58	9		T112	12
auto[0]	values[5]	values[2]	189	1			T52	16		T58	9		T235	11
auto[0]	values[5]	values[3]	131	1			T58	11		T321	10		T194	11
auto[0]	values[5]	values[4]	599	1			T60	13		T61	12		T58	9
auto[0]	values[5]	values[5]	325	1			T58	32		T322	6		T194	10
auto[0]	values[5]	values[6]	204	1			T264	6		T198	14		T269	16
auto[0]	values[5]	values[7]	314	1			T8	4		T323	2		T324	18
auto[0]	values[6]	values[0]	375	1			T224	12		T325	14		T219	16
auto[0]	values[6]	values[1]	214	1			T284	10		T235	25		T251	10
auto[0]	values[6]	values[2]	173	1			T294	6		T247	11		T67	9
auto[0]	values[6]	values[3]	217	1			T54	8		T68	15		T191	11
auto[0]	values[6]	values[4]	598	1			T7	2		T195	20		T217	26
auto[0]	values[6]	values[5]	248	1			T293	4		T61	24		T229	13
auto[0]	values[6]	values[6]	262	1			T326	22		T220	13		T327	67
auto[0]	values[6]	values[7]	163	1			T237	24		T187	7		T328	6
auto[0]	values[7]	values[0]	175	1			T58	17		T247	9		T229	16
auto[0]	values[7]	values[1]	544	1			T117	20		T228	9		T60	137
auto[0]	values[7]	values[2]	202	1			T194	9		T255	14		T251	45
auto[0]	values[7]	values[3]	302	1			T51	10		T327	12		T329	10
auto[0]	values[7]	values[4]	160	1			T67	12		T224	13		T330	12
auto[0]	values[7]	values[5]	229	1			T61	79		T224	13		T331	10
auto[0]	values[7]	values[6]	408	1			T51	13		T196	18		T86	18
auto[0]	values[7]	values[7]	97	1			T68	7		T301	7		T305	13
auto[1]	values[0]	values[0]	216	1			T58	6		T65	9		T233	71
auto[1]	values[0]	values[1]	107	1			T197	8		T230	8		T332	10
auto[1]	values[0]	values[2]	163	1			T191	34		T233	17		T194	7
auto[1]	values[0]	values[3]	225	1			T60	7		T191	7		T186	7
auto[1]	values[0]	values[4]	123	1			T227	6		T224	20		T333	16
auto[1]	values[0]	values[5]	138	1			T67	9		T186	12		T164	13
auto[1]	values[0]	values[6]	66	1			T60	10		T65	6		T334	12
auto[1]	values[0]	values[7]	156	1			T19	10		T67	28		T224	4
auto[1]	values[1]	values[0]	269	1			T254	14		T233	6		T301	10
auto[1]	values[1]	values[1]	95	1			T224	7		T255	11		T335	5
auto[1]	values[1]	values[2]	329	1			T252	5		T233	7		T220	6
auto[1]	values[1]	values[3]	148	1			T191	14		T237	11		T230	8
auto[1]	values[1]	values[4]	222	1			T51	10		T118	21		T224	8
auto[1]	values[1]	values[5]	233	1			T68	9		T305	23		T334	9
auto[1]	values[1]	values[6]	152	1			T47	6		T251	15		T336	5
auto[1]	values[1]	values[7]	201	1			T62	7		T305	9		T327	8
auto[1]	values[2]	values[0]	145	1			T337	14		T224	17		T307	8
auto[1]	values[2]	values[1]	265	1			T247	7		T66	10		T68	13
auto[1]	values[2]	values[2]	175	1			T61	8		T65	9		T67	11
auto[1]	values[2]	values[3]	450	1			T34	24		T61	6		T224	175
auto[1]	values[2]	values[4]	207	1			T235	8		T338	15		T269	93
auto[1]	values[2]	values[5]	188	1			T339	26		T194	6		T255	42
auto[1]	values[2]	values[6]	265	1			T60	77		T224	63		T220	10
auto[1]	values[2]	values[7]	223	1			T58	18		T233	62		T186	11
auto[1]	values[3]	values[0]	162	1			T68	7		T235	5		T251	8
auto[1]	values[3]	values[1]	211	1			T57	4		T68	12		T230	12
auto[1]	values[3]	values[2]	343	1			T216	6		T58	178		T290	22
auto[1]	values[3]	values[3]	279	1			T229	8		T255	8		T220	10
auto[1]	values[3]	values[4]	197	1			T194	5		T235	9		T268	14
auto[1]	values[3]	values[5]	177	1			T340	14		T313	24		T239	12
auto[1]	values[3]	values[6]	441	1			T247	7		T68	8		T194	2
auto[1]	values[3]	values[7]	138	1			T34	7		T194	6		T255	12
auto[1]	values[4]	values[0]	210	1			T235	10		T230	13		T341	87
auto[1]	values[4]	values[1]	201	1			T61	6		T224	12		T233	9
auto[1]	values[4]	values[2]	236	1			T116	4		T65	9		T68	8
auto[1]	values[4]	values[3]	204	1			T118	12		T224	10		T235	45
auto[1]	values[4]	values[4]	150	1			T342	2		T343	12		T233	2
auto[1]	values[4]	values[5]	176	1			T65	8		T68	12		T198	26
auto[1]	values[4]	values[6]	149	1			T194	26		T286	14		T230	7
auto[1]	values[4]	values[7]	270	1			T233	107		T301	10		T344	10
auto[1]	values[5]	values[0]	233	1			T60	6		T68	10		T164	9
auto[1]	values[5]	values[1]	91	1			T58	11		T193	9		T345	14
auto[1]	values[5]	values[2]	186	1			T58	12		T63	24		T235	9
auto[1]	values[5]	values[3]	92	1			T58	11		T194	9		T246	18
auto[1]	values[5]	values[4]	371	1			T60	7		T61	8		T58	12
auto[1]	values[5]	values[5]	269	1			T58	3		T194	10		T220	21
auto[1]	values[5]	values[6]	149	1			T198	6		T269	4		T346	16
auto[1]	values[5]	values[7]	215	1			T65	12		T251	72		T237	8
auto[1]	values[6]	values[0]	139	1			T224	15		T219	6		T232	9
auto[1]	values[6]	values[1]	115	1			T235	6		T251	10		T232	18
auto[1]	values[6]	values[2]	164	1			T247	9		T67	11		T301	10
auto[1]	values[6]	values[3]	182	1			T68	5		T191	67		T301	8
auto[1]	values[6]	values[4]	218	1			T194	9		T277	50		T251	7
auto[1]	values[6]	values[5]	185	1			T61	9		T229	7		T194	9
auto[1]	values[6]	values[6]	188	1			T220	7		T327	1		T347	8
auto[1]	values[6]	values[7]	268	1			T237	13		T348	20		T187	13
auto[1]	values[7]	values[0]	144	1			T16	20		T55	14		T58	9
auto[1]	values[7]	values[1]	399	1			T228	11		T60	9		T58	122
auto[1]	values[7]	values[2]	97	1			T194	11		T349	16		T255	6
auto[1]	values[7]	values[3]	192	1			T51	10		T327	8		T329	10
auto[1]	values[7]	values[4]	97	1			T67	13		T224	7		T305	6
auto[1]	values[7]	values[5]	326	1			T61	4		T224	16		T269	121
auto[1]	values[7]	values[6]	234	1			T51	11		T277	17		T240	14
auto[1]	values[7]	values[7]	73	1			T68	13		T301	13		T305	7