Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	438	1			T7	2		T46	2		T54	6
auto[ReadAddrCrossIntoMailbox]	290	1			T51	2		T58	2		T247	1
auto[ReadAddrCrossOutOfMailbox]	269	1			T8	4		T51	1		T60	1
auto[ReadAddrCrossAllMailbox]	205	1			T51	3		T61	1		T58	3
auto[ReadAddrOutsideMailbox]	3378	1			T15	4		T16	4		T19	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2238

1

T7

1

T8

2

T15

2

auto[1]

2342

1

T7

1

T8

2

T15

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	835	1			T8	2		T15	4		T16	2
read_ops[0x0b]	771	1			T40	2		T54	2		T51	2
read_ops[0x3b]	753	1			T16	2		T55	2		T195	2
read_ops[0x6b]	751	1			T40	2		T46	2		T95	2
read_ops[0xbb]	712	1			T7	2		T8	2		T59	2
read_ops[0xeb]	758	1			T46	2		T115	2		T116	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T54	1		T227	1		T253	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T54	1		T60	1		T253	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T288	1		T68	2		T224	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T51	1		T288	1		T224	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T8	1		T68	1		T197	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T8	1		T60	1		T58	3
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T191	2		T279	1		T266	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T279	1		T233	1		T194	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	323	1			T15	2		T16	1		T19	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	304	1			T15	2		T16	1		T19	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T54	1		T61	1		T221	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T54	1		T221	1		T68	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T301	1		T255	1		T351	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T51	1		T67	1		T68	3
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T194	1		T262	1		T251	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T62	1		T68	1		T224	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T257	2		T194	2		T220	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T257	2		T313	1		T230	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	260	1			T40	1		T51	1		T195	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	306	1			T40	1		T195	1		T34	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T264	3		T224	1		T265	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T264	3		T68	1		T197	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T230	1		T232	1		T245	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T65	1		T301	1		T305	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T247	1		T224	1		T235	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T266	2		T220	2		T305	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T67	1		T235	2		T251	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T68	1		T233	1		T269	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	286	1			T16	1		T55	1		T195	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	267	1			T16	1		T55	1		T195	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T46	1		T54	1		T58	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T46	1		T54	1		T58	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T253	1		T67	1		T191	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T58	1		T247	1		T253	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T194	2		T235	1		T255	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T51	1		T62	1		T198	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T61	1		T301	1		T220	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T51	1		T58	1		T68	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	269	1			T40	1		T95	1		T56	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	278	1			T40	1		T95	1		T56	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T7	1		T65	1		T224	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T7	1		T68	2		T191	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T58	1		T62	1		T65	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T198	1		T194	1		T301	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T8	1		T253	1		T220	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T8	1		T253	1		T118	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T51	1		T262	1		T266	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T58	1		T65	1		T262	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	261	1			T59	1		T195	2		T34	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	262	1			T59	1		T51	2		T195	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T265	1		T279	1		T235	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T51	1		T191	1		T224	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T227	1		T279	2		T313	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T67	1		T224	1		T279	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T68	1		T279	1		T233	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T197	1		T279	1		T233	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T288	1		T68	1		T197	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T51	1		T58	1		T288	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	291	1			T46	1		T115	1		T116	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	271	1			T46	1		T115	1		T116	1