Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3757	1			T8	4		T40	20		T56	14
values[1]	3781	1			T6	2		T15	207		T19	10
values[2]	3838	1			T52	16		T95	2		T272	2
values[3]	3711	1			T16	20		T18	6		T46	6
values[4]	3920	1			T20	14		T192	8		T59	116
values[5]	4289	1			T53	6		T57	4		T96	2
values[6]	3179	1			T7	2		T114	2		T51	41
values[7]	3539	1			T116	4		T50	20		T54	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3021	1			T19	10		T293	4		T51	24
values[1]	3720	1			T16	20		T56	14		T51	21
values[2]	3901	1			T6	2		T15	207		T40	20
values[3]	3206	1			T18	6		T115	16		T192	8
values[4]	3883	1			T95	2		T59	116		T114	2
values[5]	4468	1			T57	4		T54	8		T228	20
values[6]	4078	1			T7	2		T8	4		T53	6
values[7]	3737	1			T20	14		T96	2		T212	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29286

1

T6

2

T7

2

T8

4

auto[1]

728

1

T16

4

T51

2

T60

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	352	1			T51	23		T218	16		T288	6
auto[0]	values[0]	values[1]	469	1			T56	14		T269	119		T239	43
auto[0]	values[0]	values[2]	384	1			T40	20		T278	20		T306	4
auto[0]	values[0]	values[3]	366	1			T315	4		T269	16		T352	4
auto[0]	values[0]	values[4]	372	1			T299	4		T67	27		T265	8
auto[0]	values[0]	values[5]	761	1			T61	20		T66	6		T233	46
auto[0]	values[0]	values[6]	444	1			T8	4		T34	39		T58	20
auto[0]	values[0]	values[7]	514	1			T117	20		T322	6		T224	92
auto[0]	values[1]	values[0]	230	1			T19	10		T353	2		T235	20
auto[0]	values[1]	values[1]	304	1			T67	37		T68	20		T182	39
auto[0]	values[1]	values[2]	531	1			T6	2		T15	207		T60	39
auto[0]	values[1]	values[3]	296	1			T115	16		T233	20		T354	52
auto[0]	values[1]	values[4]	714	1			T216	6		T60	19		T62	18
auto[0]	values[1]	values[5]	454	1			T65	38		T219	22		T237	20
auto[0]	values[1]	values[6]	441	1			T55	14		T266	28		T220	59
auto[0]	values[1]	values[7]	704	1			T297	2		T61	53		T58	188
auto[0]	values[2]	values[0]	403	1			T272	2		T303	4		T220	24
auto[0]	values[2]	values[1]	537	1			T58	20		T224	19		T233	19
auto[0]	values[2]	values[2]	430	1			T52	16		T68	19		T224	18
auto[0]	values[2]	values[3]	455	1			T34	36		T65	20		T197	15
auto[0]	values[2]	values[4]	399	1			T95	2		T67	25		T68	20
auto[0]	values[2]	values[5]	690	1			T58	25		T318	8		T316	102
auto[0]	values[2]	values[6]	397	1			T273	14		T230	20		T245	37
auto[0]	values[2]	values[7]	437	1			T60	95		T247	20		T321	10
auto[0]	values[3]	values[0]	404	1			T293	4		T47	6		T221	4
auto[0]	values[3]	values[1]	460	1			T16	16		T60	20		T65	19
auto[0]	values[3]	values[2]	450	1			T233	78		T194	18		T255	49
auto[0]	values[3]	values[3]	389	1			T18	6		T294	6		T213	8
auto[0]	values[3]	values[4]	609	1			T60	146		T58	32		T65	20
auto[0]	values[3]	values[5]	502	1			T254	14		T118	20		T229	22
auto[0]	values[3]	values[6]	510	1			T46	6		T196	18		T60	20
auto[0]	values[3]	values[7]	302	1			T212	10		T225	24		T337	14
auto[0]	values[4]	values[0]	426	1			T118	20		T86	18		T233	20
auto[0]	values[4]	values[1]	593	1			T233	81		T235	30		T340	14
auto[0]	values[4]	values[2]	637	1			T58	20		T252	20		T301	20
auto[0]	values[4]	values[3]	424	1			T192	8		T191	22		T224	20
auto[0]	values[4]	values[4]	491	1			T59	116		T247	20		T191	40
auto[0]	values[4]	values[5]	384	1			T247	20		T68	20		T235	63
auto[0]	values[4]	values[6]	423	1			T61	20		T301	20		T220	20
auto[0]	values[4]	values[7]	474	1			T20	14		T287	14		T224	183
auto[0]	values[5]	values[0]	456	1			T63	20		T222	2		T224	20
auto[0]	values[5]	values[1]	437	1			T264	6		T253	20		T224	20
auto[0]	values[5]	values[2]	429	1			T195	20		T101	36		T68	20
auto[0]	values[5]	values[3]	586	1			T194	18		T304	12		T305	49
auto[0]	values[5]	values[4]	418	1			T324	18		T118	20		T194	19
auto[0]	values[5]	values[5]	701	1			T57	4		T247	20		T68	20
auto[0]	values[5]	values[6]	783	1			T53	6		T110	10		T58	91
auto[0]	values[5]	values[7]	372	1			T96	2		T349	12		T307	20
auto[0]	values[6]	values[0]	239	1			T247	20		T191	28		T355	14
auto[0]	values[6]	values[1]	458	1			T51	21		T58	76		T214	44
auto[0]	values[6]	values[2]	523	1			T257	8		T301	19		T239	20
auto[0]	values[6]	values[3]	266	1			T51	19		T68	20		T356	12
auto[0]	values[6]	values[4]	364	1			T114	2		T61	33		T314	22
auto[0]	values[6]	values[5]	284	1			T343	12		T235	30		T275	12
auto[0]	values[6]	values[6]	382	1			T7	2		T298	2		T234	16
auto[0]	values[6]	values[7]	577	1			T194	19		T235	99		T286	12
auto[0]	values[7]	values[0]	419	1			T296	2		T233	20		T235	190
auto[0]	values[7]	values[1]	377	1			T224	26		T357	16		T233	20
auto[0]	values[7]	values[2]	411	1			T50	20		T358	14		T233	71
auto[0]	values[7]	values[3]	336	1			T116	4		T255	20		T240	20
auto[0]	values[7]	values[4]	436	1			T323	2		T308	2		T262	12
auto[0]	values[7]	values[5]	599	1			T54	8		T228	20		T191	106
auto[0]	values[7]	values[6]	599	1			T58	32		T67	18		T233	101
auto[0]	values[7]	values[7]	272	1			T58	21		T311	8		T235	22
auto[1]	values[0]	values[0]	11	1			T51	1		T235	1		T359	2
auto[1]	values[0]	values[1]	12	1			T269	3		T237	1		T230	4
auto[1]	values[0]	values[2]	11	1			T220	1		T334	2		T336	2
auto[1]	values[0]	values[3]	9	1			T269	4		T241	1		T360	2
auto[1]	values[0]	values[4]	11	1			T67	2		T336	2		T246	1
auto[1]	values[0]	values[5]	21	1			T66	4		T233	2		T220	1
auto[1]	values[0]	values[6]	10	1			T197	2		T345	2		T361	1
auto[1]	values[0]	values[7]	10	1			T224	1		T261	1		T251	1
auto[1]	values[1]	values[0]	13	1			T259	1		T362	4		T363	1
auto[1]	values[1]	values[1]	13	1			T67	1		T182	4		T220	3
auto[1]	values[1]	values[2]	18	1			T60	1		T186	1		T364	2
auto[1]	values[1]	values[3]	5	1			T365	3		T366	1		T367	1
auto[1]	values[1]	values[4]	19	1			T60	1		T62	2		T239	2
auto[1]	values[1]	values[5]	8	1			T65	2		T368	2		T369	4
auto[1]	values[1]	values[6]	13	1			T220	2		T370	2		T371	1
auto[1]	values[1]	values[7]	18	1			T58	1		T313	1		T251	2
auto[1]	values[2]	values[0]	13	1			T220	2		T305	1		T372	1
auto[1]	values[2]	values[1]	16	1			T58	2		T224	1		T233	1
auto[1]	values[2]	values[2]	11	1			T68	1		T224	2		T373	3
auto[1]	values[2]	values[3]	20	1			T197	5		T338	1		T269	3
auto[1]	values[2]	values[4]	1	1			T336	1		-	-		-	-
auto[1]	values[2]	values[5]	12	1			T58	1		T239	2		T259	3
auto[1]	values[2]	values[6]	8	1			T245	3		T359	1		T374	1
auto[1]	values[2]	values[7]	9	1			T186	1		T375	1		T359	1
auto[1]	values[3]	values[0]	10	1			T224	1		T232	2		T245	2
auto[1]	values[3]	values[1]	12	1			T16	4		T65	1		T232	1
auto[1]	values[3]	values[2]	18	1			T194	2		T255	3		T269	3
auto[1]	values[3]	values[3]	13	1			T230	1		T341	4		T376	1
auto[1]	values[3]	values[4]	8	1			T58	3		T191	1		T377	2
auto[1]	values[3]	values[5]	6	1			T370	1		T371	1		T378	1
auto[1]	values[3]	values[6]	15	1			T198	2		T220	3		T241	1
auto[1]	values[3]	values[7]	3	1			T379	1		T380	2		-	-
auto[1]	values[4]	values[0]	10	1			T239	2		T187	1		T360	2
auto[1]	values[4]	values[1]	9	1			T233	2		T235	1		T336	1
auto[1]	values[4]	values[2]	10	1			T58	1		T305	1		T251	1
auto[1]	values[4]	values[3]	9	1			T235	2		T255	1		T305	2
auto[1]	values[4]	values[4]	2	1			T229	2		-	-		-	-
auto[1]	values[4]	values[5]	9	1			T246	1		T241	8		-	-
auto[1]	values[4]	values[6]	10	1			T246	2		T259	3		T381	2
auto[1]	values[4]	values[7]	9	1			T224	3		T194	1		T235	2
auto[1]	values[5]	values[0]	16	1			T63	4		T240	2		T232	2
auto[1]	values[5]	values[1]	7	1			T360	1		T374	1		T381	1
auto[1]	values[5]	values[2]	9	1			T327	2		T371	4		T380	3
auto[1]	values[5]	values[3]	22	1			T194	2		T305	2		T277	1
auto[1]	values[5]	values[4]	11	1			T194	1		T187	1		T375	1
auto[1]	values[5]	values[5]	10	1			T232	1		T187	1		T360	2
auto[1]	values[5]	values[6]	19	1			T58	4		T224	1		T382	1
auto[1]	values[5]	values[7]	13	1			T349	4		T338	1		T220	1
auto[1]	values[6]	values[0]	8	1			T245	5		T335	1		T371	2
auto[1]	values[6]	values[1]	5	1			T193	1		T230	2		T341	2
auto[1]	values[6]	values[2]	18	1			T301	1		T230	4		T240	2
auto[1]	values[6]	values[3]	4	1			T51	1		T260	1		T383	2
auto[1]	values[6]	values[4]	14	1			T64	4		T185	2		T186	1
auto[1]	values[6]	values[5]	17	1			T235	1		T230	4		T371	1
auto[1]	values[6]	values[6]	6	1			T194	1		T301	1		T186	2
auto[1]	values[6]	values[7]	14	1			T194	1		T286	2		T251	2
auto[1]	values[7]	values[0]	11	1			T235	1		T277	3		T359	1
auto[1]	values[7]	values[1]	11	1			T224	1		T357	4		T194	3
auto[1]	values[7]	values[2]	11	1			T233	2		T230	2		T368	1
auto[1]	values[7]	values[3]	6	1			T384	3		T368	1		T385	1
auto[1]	values[7]	values[4]	14	1			T232	1		T246	1		T341	2
auto[1]	values[7]	values[5]	10	1			T194	3		T220	1		T251	1
auto[1]	values[7]	values[6]	18	1			T67	2		T233	1		T237	1
auto[1]	values[7]	values[7]	9	1			T58	1		T164	3		T386	4