Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::spi_device_buffer_boundary_cg

Group : spi_device_env_pkg::spi_device_env_cov::spi_device_buffer_boundary_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::spi_device_buffer_boundary_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::spi_device_buffer_boundary_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_flip_position	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Summary for Variable cp_flip_position

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_flip_position

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92

1

T45

3

T49

1

T174

3

auto[1]

33

1

T45

2

T49

1

T174

1

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Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	11	1			T282	4		T256	2		T387	2
read_ops[0x0b]	31	1			T45	2		T49	2		T174	4
read_ops[0x3b]	21	1			T282	4		T270	4		T388	2
read_ops[0x6b]	6	1			T389	2		T388	3		T390	1
read_ops[0xbb]	26	1			T45	2		T175	6		T256	2
read_ops[0xeb]	30	1			T45	1		T256	4		T391	4