Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	847	1			T22	7		T34	27		T35	7
all_values[1]	847	1			T22	7		T34	27		T35	7
all_values[2]	847	1			T22	7		T34	27		T35	7
all_values[3]	847	1			T22	7		T34	27		T35	7
all_values[4]	847	1			T22	7		T34	27		T35	7
all_values[5]	847	1			T22	7		T34	27		T35	7
all_values[6]	847	1			T22	7		T34	27		T35	7
all_values[7]	847	1			T22	7		T34	27		T35	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3542

1

T22

33

T34

117

T35

25

auto[1]

3234

1

T22

23

T34

99

T35

31

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2701

1

T22

21

T34

70

T35

22

auto[1]

4075

1

T22

35

T34

146

T35

34

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3857

1

T22

33

T34

117

T35

28

auto[1]

2919

1

T22

23

T34

99

T35

28

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	161	1			T22	1		T34	1		T35	2
all_values[0]	auto[0]	auto[0]	auto[1]	86	1			T34	5		T190	3		T191	1
all_values[0]	auto[0]	auto[1]	auto[0]	161	1			T34	4		T35	3		T37	5
all_values[0]	auto[0]	auto[1]	auto[1]	90	1			T22	1		T34	4		T180	1
all_values[0]	auto[1]	auto[0]	auto[1]	183	1			T22	4		T34	8		T35	2
all_values[0]	auto[1]	auto[1]	auto[1]	166	1			T22	1		T34	5		T180	1
all_values[1]	auto[0]	auto[0]	auto[0]	169	1			T22	2		T34	3		T35	2
all_values[1]	auto[0]	auto[0]	auto[1]	89	1			T22	2		T34	5		T35	1
all_values[1]	auto[0]	auto[1]	auto[0]	162	1			T22	1		T35	2		T37	2
all_values[1]	auto[0]	auto[1]	auto[1]	77	1			T34	5		T37	1		T181	2
all_values[1]	auto[1]	auto[0]	auto[1]	192	1			T22	1		T34	10		T35	1
all_values[1]	auto[1]	auto[1]	auto[1]	158	1			T22	1		T34	4		T35	1
all_values[2]	auto[0]	auto[0]	auto[0]	165	1			T22	1		T34	8		T35	3
all_values[2]	auto[0]	auto[0]	auto[1]	79	1			T22	1		T34	3		T181	1
all_values[2]	auto[0]	auto[1]	auto[0]	152	1			T35	1		T180	3		T181	1
all_values[2]	auto[0]	auto[1]	auto[1]	96	1			T34	6		T37	1		T190	3
all_values[2]	auto[1]	auto[0]	auto[1]	195	1			T22	2		T34	4		T35	2
all_values[2]	auto[1]	auto[1]	auto[1]	160	1			T22	3		T34	6		T35	1
all_values[3]	auto[0]	auto[0]	auto[0]	150	1			T22	3		T34	2		T35	2
all_values[3]	auto[0]	auto[0]	auto[1]	82	1			T34	3		T190	2		T181	2
all_values[3]	auto[0]	auto[1]	auto[0]	152	1			T22	3		T34	7		T37	2
all_values[3]	auto[0]	auto[1]	auto[1]	90	1			T35	1		T37	2		T181	1
all_values[3]	auto[1]	auto[0]	auto[1]	208	1			T34	6		T35	1		T37	2
all_values[3]	auto[1]	auto[1]	auto[1]	165	1			T22	1		T34	9		T35	3
all_values[4]	auto[0]	auto[0]	auto[0]	209	1			T22	3		T34	12		T35	1
all_values[4]	auto[0]	auto[0]	auto[1]	61	1			T22	1		T34	1		T180	1
all_values[4]	auto[0]	auto[1]	auto[0]	136	1			T34	4		T35	2		T37	3
all_values[4]	auto[0]	auto[1]	auto[1]	82	1			T22	1		T34	1		T35	2
all_values[4]	auto[1]	auto[0]	auto[1]	182	1			T22	2		T34	4		T35	2
all_values[4]	auto[1]	auto[1]	auto[1]	177	1			T34	5		T37	1		T190	2
all_values[5]	auto[0]	auto[0]	auto[0]	244	1			T22	2		T34	8		T35	1
all_values[5]	auto[0]	auto[1]	auto[0]	224	1			T22	1		T34	7		T35	1
all_values[5]	auto[1]	auto[0]	auto[1]	202	1			T22	1		T34	6		T37	3
all_values[5]	auto[1]	auto[1]	auto[1]	177	1			T22	3		T34	6		T35	5
all_values[6]	auto[0]	auto[0]	auto[0]	174	1			T22	1		T34	3		T37	4
all_values[6]	auto[0]	auto[0]	auto[1]	80	1			T34	3		T35	1		T180	1
all_values[6]	auto[0]	auto[1]	auto[0]	154	1			T22	2		T34	5		T35	1
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T22	2		T34	4		T37	1
all_values[6]	auto[1]	auto[0]	auto[1]	194	1			T22	1		T34	10		T35	3
all_values[6]	auto[1]	auto[1]	auto[1]	170	1			T22	1		T34	2		T35	2
all_values[7]	auto[0]	auto[0]	auto[0]	144	1			T22	1		T34	4		T37	1
all_values[7]	auto[0]	auto[0]	auto[1]	89	1			T22	3		T34	2		T37	1
all_values[7]	auto[0]	auto[1]	auto[0]	144	1			T34	2		T35	1		T190	1
all_values[7]	auto[0]	auto[1]	auto[1]	80	1			T22	1		T34	5		T35	1
all_values[7]	auto[1]	auto[0]	auto[1]	204	1			T22	1		T34	6		T35	1
all_values[7]	auto[1]	auto[1]	auto[1]	186	1			T22	1		T34	8		T35	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal