Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1864

1

T4

4

T5

1

T9

27

auto[1]

1942

1

T4

5

T9

18

T14

7

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2058

1

T5

1

T25

9

T27

4

auto[1]

1748

1

T4

9

T9

45

T14

13

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3043

1

T4

9

T9

45

T14

13

auto[1]

763

1

T5

1

T25

2

T27

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	732	1			T4	1		T9	10		T14	1
valid[1]	747	1			T4	2		T9	8		T14	5
valid[2]	763	1			T4	1		T9	16		T14	5
valid[3]	783	1			T4	5		T5	1		T9	5
valid[4]	781	1			T9	6		T25	2		T26	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	123	1			T25	1		T69	2		T72	1
auto[0]	auto[0]	valid[0]	auto[1]	172	1			T4	1		T9	7		T29	1
auto[0]	auto[0]	valid[1]	auto[0]	111	1			T25	1		T71	1		T130	2
auto[0]	auto[0]	valid[1]	auto[1]	164	1			T4	1		T9	4		T14	2
auto[0]	auto[0]	valid[2]	auto[0]	124	1			T27	1		T71	1		T73	1
auto[0]	auto[0]	valid[2]	auto[1]	187	1			T9	9		T14	3		T26	3
auto[0]	auto[0]	valid[3]	auto[0]	138	1			T69	1		T72	1		T51	1
auto[0]	auto[0]	valid[3]	auto[1]	158	1			T4	2		T9	3		T14	1
auto[0]	auto[0]	valid[4]	auto[0]	127	1			T25	1		T69	1		T51	1
auto[0]	auto[0]	valid[4]	auto[1]	168	1			T9	4		T26	3		T31	3
auto[0]	auto[1]	valid[0]	auto[0]	117	1			T25	2		T69	2		T72	1
auto[0]	auto[1]	valid[0]	auto[1]	173	1			T9	3		T14	1		T26	4
auto[0]	auto[1]	valid[1]	auto[0]	132	1			T25	1		T73	1		T403	2
auto[0]	auto[1]	valid[1]	auto[1]	176	1			T4	1		T9	4		T14	3
auto[0]	auto[1]	valid[2]	auto[0]	118	1			T27	1		T71	1		T72	1
auto[0]	auto[1]	valid[2]	auto[1]	184	1			T4	1		T9	7		T14	2
auto[0]	auto[1]	valid[3]	auto[0]	161	1			T71	1		T72	1		T51	1
auto[0]	auto[1]	valid[3]	auto[1]	180	1			T4	3		T9	2		T14	1
auto[0]	auto[1]	valid[4]	auto[0]	144	1			T25	1		T71	1		T73	1
auto[0]	auto[1]	valid[4]	auto[1]	186	1			T9	2		T26	1		T29	1
auto[1]	auto[0]	valid[0]	auto[0]	72	1			T71	1		T130	2		T34	2
auto[1]	auto[0]	valid[1]	auto[0]	75	1			T25	1		T403	2		T393	1
auto[1]	auto[0]	valid[2]	auto[0]	76	1			T71	1		T51	3		T403	1
auto[1]	auto[0]	valid[3]	auto[0]	84	1			T5	1		T69	1		T73	3
auto[1]	auto[0]	valid[4]	auto[0]	85	1			T69	1		T72	1		T51	1
auto[1]	auto[1]	valid[0]	auto[0]	75	1			T25	1		T69	1		T73	1
auto[1]	auto[1]	valid[1]	auto[0]	89	1			T27	1		T403	1		T130	1
auto[1]	auto[1]	valid[2]	auto[0]	74	1			T72	1		T51	1		T130	1
auto[1]	auto[1]	valid[3]	auto[0]	62	1			T27	1		T71	1		T51	1
auto[1]	auto[1]	valid[4]	auto[0]	71	1			T72	1		T403	2		T35	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal