Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51124

1

T5

13

T13

1

T25

260

auto[1]

18077

1

T4

9

T9

506

T14

13

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50598

1

T4

9

T5

6

T9

506

auto[1]

18603

1

T5

7

T25

96

T27

39

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35598	1			T4	9		T5	7		T9	261
others[1]	6002	1			T9	46		T13	1		T25	30
others[2]	5827	1			T9	48		T25	24		T26	23
others[3]	6512	1			T5	3		T9	41		T25	30
interest[1]	3842	1			T5	1		T9	26		T25	12
interest[4]	23385	1			T4	9		T5	3		T9	191
interest[64]	11420	1			T5	2		T9	84		T25	40

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16783	1			T5	4		T25	81		T27	36
auto[0]	auto[0]	others[1]	2817	1			T13	1		T25	19		T27	5
auto[0]	auto[0]	others[2]	2701	1			T25	15		T27	7		T69	20
auto[0]	auto[0]	others[3]	3084	1			T25	19		T27	4		T69	26
auto[0]	auto[0]	interest[1]	1797	1			T25	6		T27	5		T69	16
auto[0]	auto[0]	interest[4]	10894	1			T5	1		T25	55		T27	31
auto[0]	auto[0]	interest[64]	5339	1			T5	2		T25	24		T27	13
auto[0]	auto[1]	others[0]	9318	1			T4	9		T9	261		T14	13
auto[0]	auto[1]	others[1]	1599	1			T9	46		T26	27		T27	1
auto[0]	auto[1]	others[2]	1481	1			T9	48		T26	23		T27	2
auto[0]	auto[1]	others[3]	1672	1			T9	41		T26	35		T27	4
auto[0]	auto[1]	interest[1]	985	1			T9	26		T26	12		T31	16
auto[0]	auto[1]	interest[4]	6274	1			T4	9		T9	191		T14	13
auto[0]	auto[1]	interest[64]	3022	1			T9	84		T26	40		T27	6
auto[1]	auto[0]	others[0]	9497	1			T5	3		T25	43		T27	17
auto[1]	auto[0]	others[1]	1586	1			T25	11		T27	1		T69	8
auto[1]	auto[0]	others[2]	1645	1			T25	9		T27	3		T30	1
auto[1]	auto[0]	others[3]	1756	1			T5	3		T25	11		T27	5
auto[1]	auto[0]	interest[1]	1060	1			T5	1		T25	6		T27	5
auto[1]	auto[0]	interest[4]	6217	1			T5	2		T25	32		T27	10
auto[1]	auto[0]	interest[64]	3059	1			T25	16		T27	8		T30	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal