Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2472849	1			T1	1		T2	1		T4	1
all_values[1]	2472849	1			T1	1		T2	1		T4	1
all_values[2]	2472849	1			T1	1		T2	1		T4	1
all_values[3]	2472849	1			T1	1		T2	1		T4	1
all_values[4]	2472849	1			T1	1		T2	1		T4	1
all_values[5]	2472849	1			T1	1		T2	1		T4	1
all_values[6]	2472849	1			T1	1		T2	1		T4	1
all_values[7]	2472849	1			T1	1		T2	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19130883

1

T1

8

T2

8

T4

8

auto[1]

651909

1

T33

63

T35

40

T36

28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19755702

1

T1

8

T2

8

T4

8

auto[1]

27090

1

T33

60

T59

3

T35

18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2324671	1			T1	1		T2	1		T4	1
all_values[0]	auto[0]	auto[1]	12677	1			T33	3		T37	7		T38	57
all_values[0]	auto[1]	auto[0]	134639	1			T33	3		T35	6		T37	7
all_values[0]	auto[1]	auto[1]	862	1			T33	5		T36	4		T37	7
all_values[1]	auto[0]	auto[0]	2421342	1			T1	1		T2	1		T4	1
all_values[1]	auto[0]	auto[1]	7959	1			T33	5		T35	2		T36	3
all_values[1]	auto[1]	auto[0]	42962	1			T33	5		T35	5		T37	9
all_values[1]	auto[1]	auto[1]	586	1			T33	3		T35	1		T36	2
all_values[2]	auto[0]	auto[0]	2440115	1			T1	1		T2	1		T4	1
all_values[2]	auto[0]	auto[1]	2974	1			T33	2		T35	1		T37	6
all_values[2]	auto[1]	auto[0]	29566	1			T33	11		T35	4		T36	2
all_values[2]	auto[1]	auto[1]	194	1			T33	5		T35	2		T36	5
all_values[3]	auto[0]	auto[0]	2338191	1			T1	1		T2	1		T4	1
all_values[3]	auto[0]	auto[1]	208	1			T33	8		T59	3		T37	8
all_values[3]	auto[1]	auto[0]	134245	1			T33	2		T35	1		T36	4
all_values[3]	auto[1]	auto[1]	205	1			T33	4		T35	2		T36	3
all_values[4]	auto[0]	auto[0]	2441764	1			T1	1		T2	1		T4	1
all_values[4]	auto[0]	auto[1]	162	1			T33	3		T35	1		T36	1
all_values[4]	auto[1]	auto[0]	30723	1			T33	2		T35	2		T36	2
all_values[4]	auto[1]	auto[1]	200	1			T33	4		T35	1		T37	7
all_values[5]	auto[0]	auto[0]	2345674	1			T1	1		T2	1		T4	1
all_values[5]	auto[0]	auto[1]	164	1			T33	3		T35	2		T36	2
all_values[5]	auto[1]	auto[0]	126835	1			T33	6		T35	3		T36	1
all_values[5]	auto[1]	auto[1]	176	1			T33	2		T35	3		T36	1
all_values[6]	auto[0]	auto[0]	2340543	1			T1	1		T2	1		T4	1
all_values[6]	auto[0]	auto[1]	193	1			T33	6		T35	1		T36	5
all_values[6]	auto[1]	auto[0]	131912	1			T33	2		T35	4		T37	5
all_values[6]	auto[1]	auto[1]	201	1			T33	3		T35	1		T37	7
all_values[7]	auto[0]	auto[0]	2454072	1			T1	1		T2	1		T4	1
all_values[7]	auto[0]	auto[1]	174	1			T33	4		T36	1		T37	4
all_values[7]	auto[1]	auto[0]	18448	1			T33	6		T35	4		T36	2
all_values[7]	auto[1]	auto[1]	155	1			T35	1		T36	2		T37	5