Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total tests in report: 1151
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
62.04 62.04 91.74 91.74 79.89 79.89 83.07 83.07 8.89 8.89 88.23 88.23 70.14 70.14 12.28 12.28 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.2345195172
70.20 8.17 93.19 1.44 82.18 2.29 83.17 0.10 44.44 35.56 90.12 1.89 74.86 4.71 23.47 11.19 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.86831544
77.16 6.95 96.04 2.85 87.34 5.16 85.33 2.17 66.67 22.22 93.93 3.81 82.43 7.57 28.37 4.90 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.198027590
81.69 4.53 97.08 1.04 88.90 1.57 87.50 2.17 88.89 22.22 95.21 1.29 84.14 1.71 30.10 1.73 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.3678551807
83.95 2.26 97.15 0.07 89.05 0.15 87.50 0.00 91.11 2.22 95.35 0.14 84.14 0.00 43.37 13.27 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.2267420693
85.97 2.02 97.54 0.39 90.06 1.01 88.88 1.38 91.11 0.00 95.77 0.42 84.29 0.14 54.16 10.79 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.2584335381
87.39 1.42 97.56 0.02 90.20 0.14 89.47 0.59 91.11 0.00 95.81 0.03 92.29 8.00 55.30 1.14 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.829454242
88.72 1.33 97.56 0.01 90.31 0.11 89.47 0.00 93.33 2.22 95.84 0.03 92.29 0.00 62.23 6.93 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.3458645436
89.42 0.71 97.69 0.13 90.31 0.00 94.19 4.72 93.33 0.00 95.92 0.08 92.29 0.00 62.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.4294659370
90.12 0.70 97.82 0.13 90.61 0.30 94.19 0.00 93.33 0.00 96.16 0.24 92.43 0.14 66.29 4.06 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1371256489
90.72 0.60 97.82 0.00 90.62 0.01 94.39 0.20 93.33 0.00 96.16 0.00 92.43 0.00 70.30 4.01 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.4086017723
91.26 0.54 97.82 0.00 90.62 0.00 94.39 0.00 93.33 0.00 96.16 0.00 92.43 0.00 74.06 3.76 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.3210062794
91.79 0.53 97.82 0.00 90.67 0.05 97.44 3.05 93.33 0.00 96.16 0.00 92.71 0.29 74.36 0.30 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.155676490
92.29 0.51 97.82 0.00 91.40 0.73 97.83 0.39 93.33 0.00 96.19 0.03 93.43 0.71 76.04 1.68 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.440686002
92.79 0.50 98.10 0.28 92.37 0.97 97.83 0.00 93.33 0.00 96.80 0.61 94.00 0.57 77.08 1.04 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.1877435488
93.28 0.49 98.10 0.00 92.41 0.04 97.83 0.00 93.33 0.00 96.82 0.02 94.00 0.00 80.45 3.37 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.19901247
93.70 0.42 98.10 0.00 92.41 0.00 97.83 0.00 93.33 0.00 96.82 0.00 94.00 0.00 83.37 2.92 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.1840446782
93.98 0.28 98.10 0.00 92.42 0.01 97.83 0.00 93.33 0.00 96.82 0.00 94.14 0.14 85.20 1.83 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.1640042436
94.22 0.24 98.10 0.00 92.42 0.00 97.83 0.00 93.33 0.00 96.82 0.00 94.14 0.00 86.88 1.68 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.4193096590
94.45 0.23 98.19 0.08 92.64 0.22 98.03 0.20 93.33 0.00 96.92 0.10 94.43 0.29 87.57 0.69 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.568854081
94.62 0.18 98.19 0.00 92.64 0.00 98.03 0.00 93.33 0.00 96.92 0.00 94.43 0.00 88.81 1.24 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1193582917
94.78 0.16 98.31 0.12 93.19 0.55 98.03 0.00 93.33 0.00 97.16 0.24 94.43 0.00 89.01 0.20 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.531997655
94.94 0.16 98.31 0.00 93.19 0.00 98.03 0.00 93.33 0.00 97.16 0.00 94.43 0.00 90.10 1.09 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.1808936801
95.08 0.14 98.31 0.00 93.19 0.00 98.03 0.00 93.33 0.00 97.16 0.00 95.43 1.00 90.10 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.1376290329
95.22 0.14 98.31 0.00 93.19 0.00 98.03 0.00 93.33 0.00 97.16 0.00 95.43 0.00 91.09 0.99 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.2491301092
95.35 0.13 98.31 0.00 93.21 0.02 98.03 0.00 93.33 0.00 97.16 0.00 95.43 0.00 91.98 0.89 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.696723858
95.45 0.10 98.31 0.00 93.21 0.00 98.03 0.00 93.33 0.00 97.16 0.00 95.43 0.00 92.67 0.69 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.4006718134
95.55 0.10 98.36 0.06 93.35 0.14 98.43 0.39 93.33 0.00 97.24 0.08 95.43 0.00 92.67 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.417205535
95.63 0.09 98.36 0.00 93.36 0.01 98.43 0.00 93.33 0.00 97.24 0.00 95.43 0.00 93.27 0.59 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.141892387
95.71 0.08 98.36 0.00 93.38 0.01 98.43 0.00 93.33 0.00 97.24 0.00 95.43 0.00 93.81 0.54 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.358591540
95.78 0.07 98.36 0.00 93.38 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.43 0.00 94.31 0.50 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.114411613
95.85 0.07 98.36 0.00 93.38 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.43 0.00 94.80 0.50 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.3268330918
95.92 0.06 98.36 0.00 93.61 0.24 98.43 0.00 93.33 0.00 97.24 0.00 95.43 0.00 95.00 0.20 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.341412147
95.97 0.06 98.36 0.00 93.61 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.43 0.00 95.40 0.40 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.822535747
96.03 0.06 98.36 0.00 93.61 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.43 0.00 95.79 0.40 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.2473824131
96.08 0.05 98.36 0.00 93.61 0.00 98.43 0.00 93.33 0.00 97.24 0.00 95.43 0.00 96.14 0.35 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2528824881
96.13 0.05 98.36 0.00 93.70 0.09 98.43 0.00 93.33 0.00 97.24 0.00 95.43 0.00 96.39 0.25 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.3152363130
96.16 0.04 98.39 0.03 93.74 0.04 98.62 0.20 93.33 0.00 97.24 0.00 95.43 0.00 96.39 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.845539628
96.20 0.04 98.39 0.00 93.74 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.43 0.00 96.63 0.25 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.4239949562
96.23 0.03 98.39 0.00 93.96 0.22 98.62 0.00 93.33 0.00 97.24 0.00 95.43 0.00 96.63 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.2292349808
96.26 0.03 98.39 0.00 93.96 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.43 0.00 96.83 0.20 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.3700603611
96.29 0.03 98.39 0.00 93.96 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.43 0.00 97.03 0.20 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.751838071
96.32 0.03 98.39 0.00 93.96 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.43 0.00 97.23 0.20 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.181554747
96.34 0.02 98.42 0.03 93.99 0.02 98.62 0.00 93.33 0.00 97.26 0.02 95.43 0.00 97.33 0.10 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.391864833
96.36 0.02 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 97.48 0.15 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.4068691469
96.38 0.02 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 97.62 0.15 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.1772921663
96.40 0.02 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 97.77 0.15 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.2033208410
96.42 0.02 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 97.92 0.15 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.1422173024
96.45 0.02 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.07 0.15 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.48755690
96.46 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.17 0.10 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.1478862149
96.47 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.27 0.10 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.2018909267
96.49 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.37 0.10 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.577834564
96.50 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.47 0.10 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.191839033
96.52 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.56 0.10 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.2650051901
96.53 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.66 0.10 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.4037722523
96.54 0.01 98.42 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.76 0.10 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.1434926057
96.56 0.01 98.42 0.00 94.01 0.02 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.81 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.852498504
96.56 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.86 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.1085775903
96.57 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.91 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.164669578
96.58 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.1254531949
96.58 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.4055932705
96.59 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2338202264
96.60 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.3662739165
96.60 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.3274559606
96.61 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.3366136958
96.62 0.01 98.42 0.00 94.01 0.00 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.2037477504
96.62 0.01 98.44 0.02 94.04 0.02 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.1349517453
96.63 0.01 98.44 0.00 94.06 0.02 98.62 0.00 93.33 0.00 97.28 0.02 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.839791859
96.63 0.01 98.44 0.00 94.08 0.02 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2483430174

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1775918772
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4039495910
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1979425199
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.1670490131
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.824042848
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.905414097
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4047659712
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.2583984369
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.1739754931
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3291312748
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3053251324
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/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.727518596
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.4182908946
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.103613081
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/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.3487226026
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3892082028
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.2822336523
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.69149777
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.1270030866
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3653378174
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2241518482
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/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.970650353
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.3955954740
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.1542622427
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3870864452
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.971049160
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.446821757
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.2620265338
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.2980270033
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/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2688095341
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/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.468566703
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.1544055036
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2371454225
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.191035860
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.1676437665
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1867715324
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.3130903438
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.2042628628
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.1586191938
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.1451971481
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.976482172
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.3068992587
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.3144326294
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.3233605970



Total test records in report: 1151
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.4294659370 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:28 AM UTC 24 15834074 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.1349517453 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:28 AM UTC 24 234021561 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.2270944614 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:29 AM UTC 24 16524457 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.2345195172 Sep 09 11:08:35 AM UTC 24 Sep 09 11:08:46 AM UTC 24 1088281757 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.3732797981 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:29 AM UTC 24 163492242 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.845539628 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:29 AM UTC 24 21280318 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.1854022891 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:29 AM UTC 24 381378266 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.2683335666 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:29 AM UTC 24 20925092 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.4070853858 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:29 AM UTC 24 161167017 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.573983713 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:29 AM UTC 24 26999634 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.568854081 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:29 AM UTC 24 68265269 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.3775732364 Sep 09 11:08:28 AM UTC 24 Sep 09 11:08:30 AM UTC 24 72631823 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.923589733 Sep 09 11:08:28 AM UTC 24 Sep 09 11:08:30 AM UTC 24 12800413 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.114309785 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:30 AM UTC 24 51222584 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.155676490 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:30 AM UTC 24 105461419 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.1793508607 Sep 09 11:08:28 AM UTC 24 Sep 09 11:08:30 AM UTC 24 323639850 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.417205535 Sep 09 11:08:28 AM UTC 24 Sep 09 11:08:30 AM UTC 24 104084641 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.781532578 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:30 AM UTC 24 213670680 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.531997655 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:31 AM UTC 24 290759138 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.3716199186 Sep 09 11:08:36 AM UTC 24 Sep 09 11:08:47 AM UTC 24 5088677492 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.187662331 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:31 AM UTC 24 120107724 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.25740995 Sep 09 11:08:29 AM UTC 24 Sep 09 11:08:31 AM UTC 24 67796661 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.2367126379 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:31 AM UTC 24 60267245 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.2136460739 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:32 AM UTC 24 478629285 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.485414494 Sep 09 11:08:41 AM UTC 24 Sep 09 11:08:46 AM UTC 24 1089462135 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.3678551807 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:32 AM UTC 24 266031496 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.4114135 Sep 09 11:08:29 AM UTC 24 Sep 09 11:08:33 AM UTC 24 553391056 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.3168376763 Sep 09 11:08:32 AM UTC 24 Sep 09 11:08:34 AM UTC 24 36680986 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.561009932 Sep 09 11:08:32 AM UTC 24 Sep 09 11:08:34 AM UTC 24 316588880 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.370850583 Sep 09 11:08:32 AM UTC 24 Sep 09 11:08:34 AM UTC 24 93446890 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.2749680264 Sep 09 11:08:32 AM UTC 24 Sep 09 11:08:34 AM UTC 24 17401425 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.1877435488 Sep 09 11:08:31 AM UTC 24 Sep 09 11:08:47 AM UTC 24 2905929774 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.2714764673 Sep 09 11:08:28 AM UTC 24 Sep 09 11:08:35 AM UTC 24 385134560 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.462600667 Sep 09 11:08:30 AM UTC 24 Sep 09 11:08:35 AM UTC 24 261204596 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.2018909267 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:35 AM UTC 24 1344164108 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.1812363435 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:35 AM UTC 24 672412107 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.3257027515 Sep 09 11:08:33 AM UTC 24 Sep 09 11:08:35 AM UTC 24 79051303 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.2774679410 Sep 09 11:08:30 AM UTC 24 Sep 09 11:08:36 AM UTC 24 183742331 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2965439368 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:38 AM UTC 24 1847200071 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.120610594 Sep 09 11:08:36 AM UTC 24 Sep 09 11:08:38 AM UTC 24 30846679 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.341412147 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:38 AM UTC 24 1111415188 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3034214261 Sep 09 11:08:34 AM UTC 24 Sep 09 11:08:38 AM UTC 24 297525167 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.1261231691 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:38 AM UTC 24 1044767874 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.3439235254 Sep 09 11:08:28 AM UTC 24 Sep 09 11:08:38 AM UTC 24 1498004510 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.111022673 Sep 09 11:08:29 AM UTC 24 Sep 09 11:08:38 AM UTC 24 448129434 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.4192113500 Sep 09 11:08:31 AM UTC 24 Sep 09 11:08:39 AM UTC 24 839914123 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.2207753531 Sep 09 11:08:28 AM UTC 24 Sep 09 11:08:39 AM UTC 24 630721193 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.3642943396 Sep 09 11:08:34 AM UTC 24 Sep 09 11:08:39 AM UTC 24 172154923 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1882245727 Sep 09 11:08:36 AM UTC 24 Sep 09 11:08:39 AM UTC 24 175769934 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.198027590 Sep 09 11:08:32 AM UTC 24 Sep 09 11:08:39 AM UTC 24 941481056 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.2193022140 Sep 09 11:08:35 AM UTC 24 Sep 09 11:08:39 AM UTC 24 92219298 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.822535747 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:39 AM UTC 24 10880291956 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.223102916 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:40 AM UTC 24 11296828947 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.3748522891 Sep 09 11:08:33 AM UTC 24 Sep 09 11:08:41 AM UTC 24 179518624 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.2342607469 Sep 09 11:08:39 AM UTC 24 Sep 09 11:08:41 AM UTC 24 34190928 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.3456845449 Sep 09 11:08:39 AM UTC 24 Sep 09 11:08:41 AM UTC 24 19342831 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.2903186935 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:41 AM UTC 24 1733823303 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.4289913093 Sep 09 11:08:39 AM UTC 24 Sep 09 11:08:42 AM UTC 24 69021637 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.1256771255 Sep 09 11:08:39 AM UTC 24 Sep 09 11:08:42 AM UTC 24 15108605 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.434111899 Sep 09 11:08:39 AM UTC 24 Sep 09 11:08:42 AM UTC 24 94057884 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.622428107 Sep 09 11:08:36 AM UTC 24 Sep 09 11:08:42 AM UTC 24 462961414 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.3652118283 Sep 09 11:08:39 AM UTC 24 Sep 09 11:08:44 AM UTC 24 632990348 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.4084106892 Sep 09 11:08:41 AM UTC 24 Sep 09 11:08:45 AM UTC 24 111076391 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.3586659654 Sep 09 11:08:43 AM UTC 24 Sep 09 11:08:46 AM UTC 24 40870283 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.3677734234 Sep 09 11:08:41 AM UTC 24 Sep 09 11:08:46 AM UTC 24 515640678 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.2579468871 Sep 09 11:08:36 AM UTC 24 Sep 09 11:08:46 AM UTC 24 862771442 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.2627025196 Sep 09 11:08:42 AM UTC 24 Sep 09 11:08:46 AM UTC 24 46351804 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.2339353143 Sep 09 11:08:41 AM UTC 24 Sep 09 11:08:47 AM UTC 24 1715666136 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.931162608 Sep 09 11:08:44 AM UTC 24 Sep 09 11:08:47 AM UTC 24 935788022 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.3831763524 Sep 09 11:08:45 AM UTC 24 Sep 09 11:08:47 AM UTC 24 12471120 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.2967825645 Sep 09 11:08:46 AM UTC 24 Sep 09 11:08:49 AM UTC 24 20981289 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.1547267741 Sep 09 11:08:41 AM UTC 24 Sep 09 11:08:49 AM UTC 24 1435087938 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.1451431529 Sep 09 11:08:47 AM UTC 24 Sep 09 11:08:49 AM UTC 24 93647262 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.4075207580 Sep 09 11:08:47 AM UTC 24 Sep 09 11:08:49 AM UTC 24 86564281 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.2635313285 Sep 09 11:08:42 AM UTC 24 Sep 09 11:08:50 AM UTC 24 3084807283 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.391864833 Sep 09 11:08:29 AM UTC 24 Sep 09 11:08:50 AM UTC 24 4104208435 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2978071847 Sep 09 11:08:29 AM UTC 24 Sep 09 11:08:51 AM UTC 24 13124650854 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.10796491 Sep 09 11:08:39 AM UTC 24 Sep 09 11:08:51 AM UTC 24 6778187387 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.2732552436 Sep 09 11:08:48 AM UTC 24 Sep 09 11:08:53 AM UTC 24 539081153 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.191035860 Sep 09 11:09:18 AM UTC 24 Sep 09 11:09:26 AM UTC 24 241797274 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.1864393178 Sep 09 11:08:30 AM UTC 24 Sep 09 11:08:53 AM UTC 24 1921220136 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.962685448 Sep 09 11:08:48 AM UTC 24 Sep 09 11:08:54 AM UTC 24 201978212 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.2415371463 Sep 09 11:08:49 AM UTC 24 Sep 09 11:08:54 AM UTC 24 96176060 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.3483660445 Sep 09 11:08:52 AM UTC 24 Sep 09 11:08:54 AM UTC 24 156247039 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.945626897 Sep 09 11:08:49 AM UTC 24 Sep 09 11:08:54 AM UTC 24 296559559 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.2086146680 Sep 09 11:08:48 AM UTC 24 Sep 09 11:08:55 AM UTC 24 136555665 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.3856370673 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:55 AM UTC 24 46113010720 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3083753345 Sep 09 11:08:47 AM UTC 24 Sep 09 11:08:56 AM UTC 24 2299966842 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.3086885315 Sep 09 11:08:54 AM UTC 24 Sep 09 11:08:56 AM UTC 24 13413335 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.1979166858 Sep 09 11:08:54 AM UTC 24 Sep 09 11:08:56 AM UTC 24 21918012 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.1356489004 Sep 09 11:08:30 AM UTC 24 Sep 09 11:08:57 AM UTC 24 15900601381 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.3284906907 Sep 09 11:08:47 AM UTC 24 Sep 09 11:08:57 AM UTC 24 813389061 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.656533636 Sep 09 11:08:54 AM UTC 24 Sep 09 11:08:57 AM UTC 24 194130295 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.1838832694 Sep 09 11:08:48 AM UTC 24 Sep 09 11:08:57 AM UTC 24 1430709846 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.908001619 Sep 09 11:08:56 AM UTC 24 Sep 09 11:08:58 AM UTC 24 394079281 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.702223030 Sep 09 11:08:50 AM UTC 24 Sep 09 11:08:58 AM UTC 24 1503528229 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.1085775903 Sep 09 11:08:27 AM UTC 24 Sep 09 11:08:59 AM UTC 24 13247309860 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.2733557211 Sep 09 11:08:56 AM UTC 24 Sep 09 11:08:59 AM UTC 24 207555951 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.86831544 Sep 09 11:08:31 AM UTC 24 Sep 09 11:09:00 AM UTC 24 5125373810 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.1322550239 Sep 09 11:09:00 AM UTC 24 Sep 09 11:09:02 AM UTC 24 99958213 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.715923548 Sep 09 11:08:57 AM UTC 24 Sep 09 11:09:02 AM UTC 24 83311662 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.2236781535 Sep 09 11:09:00 AM UTC 24 Sep 09 11:09:02 AM UTC 24 242341687 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2674964681 Sep 09 11:08:56 AM UTC 24 Sep 09 11:09:02 AM UTC 24 746957139 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.3071844252 Sep 09 11:08:32 AM UTC 24 Sep 09 11:09:03 AM UTC 24 17392020626 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.4182908946 Sep 09 11:09:01 AM UTC 24 Sep 09 11:09:03 AM UTC 24 24584681 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.259392197 Sep 09 11:08:39 AM UTC 24 Sep 09 11:09:03 AM UTC 24 2881271550 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.2299147673 Sep 09 11:08:57 AM UTC 24 Sep 09 11:09:04 AM UTC 24 266199241 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.852498504 Sep 09 11:08:48 AM UTC 24 Sep 09 11:09:05 AM UTC 24 20706757671 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.1801130225 Sep 09 11:09:03 AM UTC 24 Sep 09 11:09:05 AM UTC 24 55086621 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.1270030866 Sep 09 11:09:03 AM UTC 24 Sep 09 11:09:05 AM UTC 24 28199203 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.3441737835 Sep 09 11:08:57 AM UTC 24 Sep 09 11:09:06 AM UTC 24 992141820 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.4259199921 Sep 09 11:08:30 AM UTC 24 Sep 09 11:09:06 AM UTC 24 15899413022 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2912037773 Sep 09 11:08:58 AM UTC 24 Sep 09 11:09:07 AM UTC 24 847712369 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.1161647091 Sep 09 11:08:57 AM UTC 24 Sep 09 11:09:07 AM UTC 24 818390185 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.2822336523 Sep 09 11:09:04 AM UTC 24 Sep 09 11:09:08 AM UTC 24 51056300 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.713033945 Sep 09 11:08:54 AM UTC 24 Sep 09 11:09:08 AM UTC 24 12389228786 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1076174849 Sep 09 11:09:13 AM UTC 24 Sep 09 11:09:22 AM UTC 24 2263816140 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.1309660222 Sep 09 11:08:57 AM UTC 24 Sep 09 11:09:09 AM UTC 24 1032251727 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3031069240 Sep 09 11:09:03 AM UTC 24 Sep 09 11:09:09 AM UTC 24 3509586219 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.69149777 Sep 09 11:09:05 AM UTC 24 Sep 09 11:09:09 AM UTC 24 160933286 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.2909331936 Sep 09 11:08:31 AM UTC 24 Sep 09 11:09:09 AM UTC 24 2265937757 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.1179089040 Sep 09 11:09:04 AM UTC 24 Sep 09 11:09:10 AM UTC 24 1039416896 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.2726510981 Sep 09 11:08:54 AM UTC 24 Sep 09 11:09:10 AM UTC 24 1212047830 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.3731415396 Sep 09 11:08:50 AM UTC 24 Sep 09 11:09:10 AM UTC 24 7311680089 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3653378174 Sep 09 11:09:04 AM UTC 24 Sep 09 11:09:11 AM UTC 24 493299453 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.758103598 Sep 09 11:09:07 AM UTC 24 Sep 09 11:09:11 AM UTC 24 226281032 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.376480854 Sep 09 11:08:42 AM UTC 24 Sep 09 11:09:11 AM UTC 24 19041658012 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.971049160 Sep 09 11:09:13 AM UTC 24 Sep 09 11:09:22 AM UTC 24 1262868038 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.2415767154 Sep 09 11:09:19 AM UTC 24 Sep 09 11:09:26 AM UTC 24 163049565 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.727518596 Sep 09 11:09:07 AM UTC 24 Sep 09 11:09:11 AM UTC 24 208905627 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.1165816635 Sep 09 11:09:09 AM UTC 24 Sep 09 11:09:11 AM UTC 24 12728297 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.3458645436 Sep 09 11:08:43 AM UTC 24 Sep 09 11:09:11 AM UTC 24 2160574938 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.3152363130 Sep 09 11:08:27 AM UTC 24 Sep 09 11:09:11 AM UTC 24 1828625541 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.2867521814 Sep 09 11:09:09 AM UTC 24 Sep 09 11:09:11 AM UTC 24 336816278 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.3955954740 Sep 09 11:09:10 AM UTC 24 Sep 09 11:09:12 AM UTC 24 16189474 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.2330219653 Sep 09 11:09:11 AM UTC 24 Sep 09 11:09:13 AM UTC 24 30322678 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.503648656 Sep 09 11:09:11 AM UTC 24 Sep 09 11:09:13 AM UTC 24 26495971 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.2980270033 Sep 09 11:09:10 AM UTC 24 Sep 09 11:09:13 AM UTC 24 111123455 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.1997379801 Sep 09 11:08:58 AM UTC 24 Sep 09 11:09:13 AM UTC 24 1505596122 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.2045461519 Sep 09 11:09:10 AM UTC 24 Sep 09 11:09:14 AM UTC 24 1077411804 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.731552440 Sep 09 11:09:12 AM UTC 24 Sep 09 11:09:14 AM UTC 24 105247669 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.3412061797 Sep 09 11:08:28 AM UTC 24 Sep 09 11:09:15 AM UTC 24 14491348570 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.3754320923 Sep 09 11:08:42 AM UTC 24 Sep 09 11:09:15 AM UTC 24 3957259940 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.1542622427 Sep 09 11:09:13 AM UTC 24 Sep 09 11:09:16 AM UTC 24 56102841 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.978845650 Sep 09 11:08:57 AM UTC 24 Sep 09 11:09:16 AM UTC 24 3349297527 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.970650353 Sep 09 11:09:12 AM UTC 24 Sep 09 11:09:16 AM UTC 24 157485128 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.1708390109 Sep 09 11:09:07 AM UTC 24 Sep 09 11:09:16 AM UTC 24 2361350582 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.2787972940 Sep 09 11:09:15 AM UTC 24 Sep 09 11:09:17 AM UTC 24 34778825 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.3295582290 Sep 09 11:09:08 AM UTC 24 Sep 09 11:09:17 AM UTC 24 1775876596 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.915403926 Sep 09 11:09:16 AM UTC 24 Sep 09 11:09:18 AM UTC 24 68470182 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.1676437665 Sep 09 11:09:16 AM UTC 24 Sep 09 11:09:18 AM UTC 24 36042950 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.3487226026 Sep 09 11:09:07 AM UTC 24 Sep 09 11:09:19 AM UTC 24 670224392 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.446821757 Sep 09 11:09:12 AM UTC 24 Sep 09 11:09:19 AM UTC 24 506458509 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.3068992587 Sep 09 11:09:17 AM UTC 24 Sep 09 11:09:19 AM UTC 24 77834343 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.3144326294 Sep 09 11:09:17 AM UTC 24 Sep 09 11:09:20 AM UTC 24 113862066 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.3947597398 Sep 09 11:09:03 AM UTC 24 Sep 09 11:09:21 AM UTC 24 4004701768 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1867715324 Sep 09 11:09:17 AM UTC 24 Sep 09 11:09:21 AM UTC 24 43560136 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.2620265338 Sep 09 11:09:12 AM UTC 24 Sep 09 11:09:26 AM UTC 24 1692365668 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.976482172 Sep 09 11:09:16 AM UTC 24 Sep 09 11:09:25 AM UTC 24 1954250220 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.3130903438 Sep 09 11:09:17 AM UTC 24 Sep 09 11:09:26 AM UTC 24 3604028887 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.3233605970 Sep 09 11:09:19 AM UTC 24 Sep 09 11:09:26 AM UTC 24 1341486342 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2241518482 Sep 09 11:09:04 AM UTC 24 Sep 09 11:09:27 AM UTC 24 11180074418 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.2995802589 Sep 09 11:09:25 AM UTC 24 Sep 09 11:09:27 AM UTC 24 35867211 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.692050616 Sep 09 11:09:26 AM UTC 24 Sep 09 11:09:28 AM UTC 24 16105092 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3892082028 Sep 09 11:09:07 AM UTC 24 Sep 09 11:09:29 AM UTC 24 8397463950 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1182089852 Sep 09 11:09:27 AM UTC 24 Sep 09 11:09:30 AM UTC 24 38375671 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.1675596171 Sep 09 11:09:27 AM UTC 24 Sep 09 11:09:30 AM UTC 24 85532811 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.206994111 Sep 09 11:09:27 AM UTC 24 Sep 09 11:09:30 AM UTC 24 177977672 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.2588986085 Sep 09 11:09:27 AM UTC 24 Sep 09 11:09:30 AM UTC 24 54990548 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.3015446823 Sep 09 11:09:12 AM UTC 24 Sep 09 11:09:30 AM UTC 24 917117291 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.3872537374 Sep 09 11:08:27 AM UTC 24 Sep 09 11:09:31 AM UTC 24 6117222322 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.495803888 Sep 09 11:09:12 AM UTC 24 Sep 09 11:09:31 AM UTC 24 14040283617 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.468566703 Sep 09 11:09:19 AM UTC 24 Sep 09 11:09:31 AM UTC 24 2734049968 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.2371454225 Sep 09 11:09:18 AM UTC 24 Sep 09 11:09:33 AM UTC 24 1069960109 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.2042628628 Sep 09 11:09:21 AM UTC 24 Sep 09 11:09:33 AM UTC 24 542966679 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.839791859 Sep 09 11:09:31 AM UTC 24 Sep 09 11:09:37 AM UTC 24 156948294 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.1451971481 Sep 09 11:09:17 AM UTC 24 Sep 09 11:09:39 AM UTC 24 1721353728 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.390461793 Sep 09 11:09:30 AM UTC 24 Sep 09 11:09:40 AM UTC 24 1183933793 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.1799316822 Sep 09 11:09:31 AM UTC 24 Sep 09 11:09:40 AM UTC 24 265173376 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.1002525805 Sep 09 11:09:28 AM UTC 24 Sep 09 11:09:42 AM UTC 24 1660047013 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2688095341 Sep 09 11:09:22 AM UTC 24 Sep 09 11:09:44 AM UTC 24 2994285918 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1371256489 Sep 09 11:08:31 AM UTC 24 Sep 09 11:09:45 AM UTC 24 3122600955 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.4239949562 Sep 09 11:09:00 AM UTC 24 Sep 09 11:09:45 AM UTC 24 1563082790 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.2586525453 Sep 09 11:09:29 AM UTC 24 Sep 09 11:09:45 AM UTC 24 2344579580 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.1591354393 Sep 09 11:09:12 AM UTC 24 Sep 09 11:09:47 AM UTC 24 6141155489 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.696723858 Sep 09 11:08:37 AM UTC 24 Sep 09 11:09:48 AM UTC 24 4519442058 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.2285131638 Sep 09 11:09:27 AM UTC 24 Sep 09 11:09:48 AM UTC 24 1788395235 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.332353562 Sep 09 11:09:32 AM UTC 24 Sep 09 11:09:48 AM UTC 24 5435331371 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.417712645 Sep 09 11:08:58 AM UTC 24 Sep 09 11:09:49 AM UTC 24 5905914860 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1353205994 Sep 09 11:08:27 AM UTC 24 Sep 09 11:09:49 AM UTC 24 82758366558 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.1776381376 Sep 09 11:08:48 AM UTC 24 Sep 09 11:09:49 AM UTC 24 5743458644 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.2267420693 Sep 09 11:08:27 AM UTC 24 Sep 09 11:09:49 AM UTC 24 28136072514 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.3976786540 Sep 09 11:09:48 AM UTC 24 Sep 09 11:09:50 AM UTC 24 19768069 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.3379841083 Sep 09 11:09:48 AM UTC 24 Sep 09 11:09:51 AM UTC 24 61052600 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.911448776 Sep 09 11:09:48 AM UTC 24 Sep 09 11:09:51 AM UTC 24 75392474 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.2840809183 Sep 09 11:09:48 AM UTC 24 Sep 09 11:09:51 AM UTC 24 62292003 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2869292789 Sep 09 11:08:52 AM UTC 24 Sep 09 11:09:51 AM UTC 24 15294537093 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.2316251380 Sep 09 11:09:48 AM UTC 24 Sep 09 11:09:51 AM UTC 24 36801687 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.3062901699 Sep 09 11:09:49 AM UTC 24 Sep 09 11:09:54 AM UTC 24 184161468 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.423010047 Sep 09 11:09:55 AM UTC 24 Sep 09 11:10:10 AM UTC 24 1093556417 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.3369231226 Sep 09 11:09:52 AM UTC 24 Sep 09 11:09:54 AM UTC 24 23254791 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.1875876314 Sep 09 11:09:52 AM UTC 24 Sep 09 11:09:54 AM UTC 24 25213101 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.164669578 Sep 09 11:09:50 AM UTC 24 Sep 09 11:09:54 AM UTC 24 168997696 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.3666989666 Sep 09 11:09:52 AM UTC 24 Sep 09 11:09:54 AM UTC 24 117856518 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.1764598321 Sep 09 11:09:52 AM UTC 24 Sep 09 11:09:54 AM UTC 24 32013461 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.1410393369 Sep 09 11:09:32 AM UTC 24 Sep 09 11:09:55 AM UTC 24 5570015396 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.2634898574 Sep 09 11:09:31 AM UTC 24 Sep 09 11:09:56 AM UTC 24 17061697838 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.2728297613 Sep 09 11:09:54 AM UTC 24 Sep 09 11:09:57 AM UTC 24 537362016 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.2267152340 Sep 09 11:09:48 AM UTC 24 Sep 09 11:09:58 AM UTC 24 7938985284 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.4088434211 Sep 09 11:09:50 AM UTC 24 Sep 09 11:09:58 AM UTC 24 1252542320 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.2809204797 Sep 09 11:09:48 AM UTC 24 Sep 09 11:09:59 AM UTC 24 2646570039 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.2609887915 Sep 09 11:09:55 AM UTC 24 Sep 09 11:09:59 AM UTC 24 112149809 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.2291414535 Sep 09 11:09:56 AM UTC 24 Sep 09 11:10:00 AM UTC 24 119503704 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.873740686 Sep 09 11:09:58 AM UTC 24 Sep 09 11:10:00 AM UTC 24 53284867 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.2718532265 Sep 09 11:09:55 AM UTC 24 Sep 09 11:10:00 AM UTC 24 457934968 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.2600917702 Sep 09 11:09:50 AM UTC 24 Sep 09 11:10:00 AM UTC 24 1335214731 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.3275985700 Sep 09 11:08:38 AM UTC 24 Sep 09 11:10:01 AM UTC 24 31327871935 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.1316433459 Sep 09 11:10:01 AM UTC 24 Sep 09 11:10:03 AM UTC 24 22206620 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.3925782298 Sep 09 11:09:50 AM UTC 24 Sep 09 11:10:04 AM UTC 24 210092669 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.1357899982 Sep 09 11:10:01 AM UTC 24 Sep 09 11:10:04 AM UTC 24 70530049 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.83370144 Sep 09 11:10:01 AM UTC 24 Sep 09 11:10:04 AM UTC 24 52353193 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.2951048739 Sep 09 11:10:02 AM UTC 24 Sep 09 11:10:05 AM UTC 24 13089206 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.1709781015 Sep 09 11:09:31 AM UTC 24 Sep 09 11:10:05 AM UTC 24 7134613324 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.1544055036 Sep 09 11:09:21 AM UTC 24 Sep 09 11:10:05 AM UTC 24 7501226163 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.1164534161 Sep 09 11:09:31 AM UTC 24 Sep 09 11:10:07 AM UTC 24 17293683724 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.974014261 Sep 09 11:10:04 AM UTC 24 Sep 09 11:10:07 AM UTC 24 95206810 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.3947089819 Sep 09 11:10:05 AM UTC 24 Sep 09 11:10:07 AM UTC 24 25731118 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.2963581721 Sep 09 11:10:04 AM UTC 24 Sep 09 11:10:09 AM UTC 24 157446957 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.1273070059 Sep 09 11:10:05 AM UTC 24 Sep 09 11:10:09 AM UTC 24 698229614 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.425960613 Sep 09 11:10:06 AM UTC 24 Sep 09 11:10:10 AM UTC 24 95825961 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.3569289816 Sep 09 11:09:59 AM UTC 24 Sep 09 11:10:10 AM UTC 24 686895277 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.3965771210 Sep 09 11:10:06 AM UTC 24 Sep 09 11:10:10 AM UTC 24 30279700 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2229560277 Sep 09 11:09:48 AM UTC 24 Sep 09 11:10:10 AM UTC 24 17278623573 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.3178422358 Sep 09 11:09:48 AM UTC 24 Sep 09 11:10:11 AM UTC 24 6349930341 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.4196973472 Sep 09 11:09:57 AM UTC 24 Sep 09 11:10:13 AM UTC 24 766984550 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.1490758794 Sep 09 11:09:50 AM UTC 24 Sep 09 11:10:13 AM UTC 24 839906528 ps
T490 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.1582345933 Sep 09 11:10:12 AM UTC 24 Sep 09 11:10:14 AM UTC 24 11497848 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.2454781814 Sep 09 11:10:12 AM UTC 24 Sep 09 11:10:14 AM UTC 24 20651730 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.232232916 Sep 09 11:10:12 AM UTC 24 Sep 09 11:10:14 AM UTC 24 120527643 ps
T493 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.3155434328 Sep 09 11:10:09 AM UTC 24 Sep 09 11:10:14 AM UTC 24 559861564 ps
T494 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.3225704330 Sep 09 11:09:52 AM UTC 24 Sep 09 11:10:14 AM UTC 24 4591228402 ps
T495 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.1091219825 Sep 09 11:10:15 AM UTC 24 Sep 09 11:10:17 AM UTC 24 51681069 ps
T496 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_rw.4065190281 Sep 09 11:10:15 AM UTC 24 Sep 09 11:10:18 AM UTC 24 279739989 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.2712486044 Sep 09 11:10:08 AM UTC 24 Sep 09 11:10:19 AM UTC 24 10091128019 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.2348353905 Sep 09 11:09:55 AM UTC 24 Sep 09 11:10:19 AM UTC 24 3702509072 ps
T497 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.3796580314 Sep 09 11:10:14 AM UTC 24 Sep 09 11:10:19 AM UTC 24 925219505 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1864709304 Sep 09 11:09:55 AM UTC 24 Sep 09 11:10:19 AM UTC 24 14949364930 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.1651809173 Sep 09 11:10:00 AM UTC 24 Sep 09 11:10:22 AM UTC 24 1596748809 ps
T498 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode.2872088935 Sep 09 11:10:08 AM UTC 24 Sep 09 11:10:22 AM UTC 24 508887644 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_intercept.228656903 Sep 09 11:10:15 AM UTC 24 Sep 09 11:10:22 AM UTC 24 164135511 ps
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