SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
98.36 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 38 | 0 | 38 | 100.00 |
Crosses | 84 | 2 | 82 | 97.62 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_addr_mode | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_addr_swap_en | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_busy | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_dummy_cycles | 9 | 0 | 9 | 100.00 | 100 | 1 | 1 | 0 | |
cp_is_flash | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_is_write | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_lanes | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_opcode | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 | |
cp_payload_swap_en | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_upload | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
cr_modeXdirXaddrXswap | 48 | 0 | 48 | 100.00 | 100 | 1 | 1 | 0 | |
cr_modeXdummyXnum_lanes | 36 | 2 | 34 | 94.44 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[SpiFlashAddrDisabled] | 34400 | 1 | T4 | 2 | T15 | 2 | T16 | 31 | ||||
auto[SpiFlashAddrCfg] | 7577 | 1 | T16 | 2 | T24 | 7 | T54 | 2 | ||||
auto[SpiFlashAddr3b] | 8814 | 1 | T16 | 2 | T22 | 8 | T23 | 3 | ||||
auto[SpiFlashAddr4b] | 7333 | 1 | T16 | 2 | T23 | 8 | T24 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 32709 | 1 | T4 | 2 | T15 | 2 | T16 | 37 | ||||
auto[1] | 25415 | 1 | T24 | 12 | T55 | 10 | T56 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 30850 | 1 | T15 | 2 | T16 | 33 | T23 | 9 | ||||
auto[1] | 27274 | 1 | T4 | 2 | T16 | 4 | T22 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 9 | 0 | 9 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 39157 | 1 | T4 | 2 | T15 | 2 | T16 | 35 | ||||
values[1] | 1038 | 1 | T107 | 2 | T108 | 6 | T66 | 2 | ||||
values[2] | 1453 | 1 | T63 | 2 | T208 | 2 | T65 | 4 | ||||
values[3] | 1413 | 1 | T24 | 2 | T55 | 2 | T63 | 2 | ||||
values[4] | 1453 | 1 | T24 | 1 | T54 | 2 | T83 | 2 | ||||
values[5] | 1372 | 1 | T22 | 4 | T65 | 4 | T209 | 6 | ||||
values[6] | 1395 | 1 | T24 | 1 | T62 | 4 | T59 | 4 | ||||
values[7] | 1362 | 1 | T56 | 4 | T208 | 2 | T107 | 2 | ||||
values[8] | 9481 | 1 | T16 | 2 | T22 | 4 | T23 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 32568 | 1 | T4 | 2 | T15 | 2 | T16 | 37 | ||||
auto[1] | 25556 | 1 | T23 | 11 | T24 | 40 | T85 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
read | 54880 | 1 | T4 | 2 | T15 | 2 | T16 | 33 | ||||
write | 3244 | 1 | T16 | 4 | T24 | 5 | T55 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | STATUS |
others | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
valids[0x0] | 18596 | 1 | T15 | 2 | T16 | 2 | T22 | 6 | ||||
valids[0x1] | 39528 | 1 | T4 | 2 | T16 | 35 | T22 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
internal_process_ops[0x9f] | 1480 | 1 | T22 | 2 | T54 | 2 | T70 | 2 | ||||
internal_process_ops[0x5a] | 1556 | 1 | T22 | 2 | T24 | 1 | T56 | 4 | ||||
internal_process_ops[0x05] | 21142 | 1 | T16 | 29 | T22 | 2 | T24 | 21 | ||||
internal_process_ops[0x35] | 1451 | 1 | T24 | 1 | T210 | 2 | T211 | 2 | ||||
internal_process_ops[0x15] | 1485 | 1 | T4 | 2 | T16 | 2 | T24 | 1 | ||||
internal_process_ops[0x03] | 984 | 1 | T23 | 3 | T55 | 2 | T81 | 4 | ||||
internal_process_ops[0x0b] | 1049 | 1 | T23 | 5 | T208 | 2 | T65 | 4 | ||||
internal_process_ops[0x3b] | 1031 | 1 | T85 | 1 | T208 | 2 | T107 | 2 | ||||
internal_process_ops[0x6b] | 1057 | 1 | T22 | 2 | T23 | 1 | T56 | 2 | ||||
internal_process_ops[0xbb] | 1038 | 1 | T23 | 2 | T56 | 4 | T63 | 2 | ||||
internal_process_ops[0xeb] | 1037 | 1 | T22 | 4 | T54 | 2 | T55 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 56586 | 1 | T4 | 2 | T15 | 2 | T16 | 37 | ||||
auto[1] | 1538 | 1 | T24 | 2 | T55 | 2 | T66 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 55747 | 1 | T4 | 2 | T15 | 2 | T16 | 35 | ||||
auto[1] | 2377 | 1 | T16 | 2 | T24 | 3 | T66 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 48 | 0 | 48 | 100.00 | |
Automatically Generated Cross Bins | 48 | 0 | 48 | 100.00 | |
User Defined Cross Bins | 0 | 0 | 0 |
cp_is_flash | cp_is_write | cp_addr_mode | cp_addr_swap_en | cp_payload_swap_en | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | read | auto[SpiFlashAddrDisabled] | auto[0] | auto[0] | 11264 | 1 | T4 | 2 | T15 | 2 | T16 | 31 | ||||
auto[0] | read | auto[SpiFlashAddrDisabled] | auto[1] | auto[0] | 7224 | 1 | T55 | 2 | T70 | 4 | T65 | 8 | ||||
auto[0] | read | auto[SpiFlashAddrCfg] | auto[0] | auto[0] | 2159 | 1 | T16 | 2 | T54 | 2 | T62 | 6 | ||||
auto[0] | read | auto[SpiFlashAddrCfg] | auto[1] | auto[0] | 1781 | 1 | T55 | 2 | T65 | 2 | T66 | 10 | ||||
auto[0] | read | auto[SpiFlashAddr3b] | auto[0] | auto[0] | 2476 | 1 | T22 | 8 | T54 | 2 | T63 | 4 | ||||
auto[0] | read | auto[SpiFlashAddr3b] | auto[1] | auto[0] | 2114 | 1 | T55 | 2 | T56 | 10 | T65 | 6 | ||||
auto[0] | read | auto[SpiFlashAddr4b] | auto[0] | auto[0] | 2124 | 1 | T83 | 4 | T208 | 8 | T209 | 6 | ||||
auto[0] | read | auto[SpiFlashAddr4b] | auto[1] | auto[0] | 1794 | 1 | T55 | 2 | T56 | 2 | T66 | 9 | ||||
auto[0] | write | auto[SpiFlashAddrDisabled] | auto[0] | auto[0] | 133 | 1 | T64 | 4 | T66 | 2 | T90 | 1 | ||||
auto[0] | write | auto[SpiFlashAddrDisabled] | auto[0] | auto[1] | 111 | 1 | T66 | 1 | T78 | 1 | T212 | 3 | ||||
auto[0] | write | auto[SpiFlashAddrDisabled] | auto[1] | auto[0] | 72 | 1 | T213 | 1 | T89 | 1 | T90 | 2 | ||||
auto[0] | write | auto[SpiFlashAddrDisabled] | auto[1] | auto[1] | 104 | 1 | T71 | 2 | T75 | 4 | T90 | 1 | ||||
auto[0] | write | auto[SpiFlashAddrCfg] | auto[0] | auto[0] | 132 | 1 | T214 | 2 | T69 | 2 | T215 | 2 | ||||
auto[0] | write | auto[SpiFlashAddrCfg] | auto[0] | auto[1] | 95 | 1 | T77 | 2 | T78 | 1 | T213 | 2 | ||||
auto[0] | write | auto[SpiFlashAddrCfg] | auto[1] | auto[0] | 107 | 1 | T52 | 3 | T76 | 1 | T216 | 1 | ||||
auto[0] | write | auto[SpiFlashAddrCfg] | auto[1] | auto[1] | 118 | 1 | T55 | 2 | T66 | 1 | T76 | 3 | ||||
auto[0] | write | auto[SpiFlashAddr3b] | auto[0] | auto[0] | 107 | 1 | T16 | 2 | T72 | 4 | T76 | 1 | ||||
auto[0] | write | auto[SpiFlashAddr3b] | auto[0] | auto[1] | 90 | 1 | T74 | 2 | T76 | 3 | T90 | 1 | ||||
auto[0] | write | auto[SpiFlashAddr3b] | auto[1] | auto[0] | 87 | 1 | T52 | 2 | T76 | 4 | T79 | 1 | ||||
auto[0] | write | auto[SpiFlashAddr3b] | auto[1] | auto[1] | 81 | 1 | T66 | 1 | T75 | 2 | T79 | 2 | ||||
auto[0] | write | auto[SpiFlashAddr4b] | auto[0] | auto[0] | 109 | 1 | T16 | 2 | T201 | 4 | T74 | 3 | ||||
auto[0] | write | auto[SpiFlashAddr4b] | auto[0] | auto[1] | 80 | 1 | T52 | 2 | T76 | 1 | T212 | 1 | ||||
auto[0] | write | auto[SpiFlashAddr4b] | auto[1] | auto[0] | 103 | 1 | T105 | 1 | T90 | 3 | T216 | 2 | ||||
auto[0] | write | auto[SpiFlashAddr4b] | auto[1] | auto[1] | 103 | 1 | T105 | 1 | T80 | 4 | T90 | 1 | ||||
auto[1] | read | auto[SpiFlashAddrDisabled] | auto[0] | auto[0] | 8356 | 1 | T24 | 25 | T61 | 33 | T57 | 45 | ||||
auto[1] | read | auto[SpiFlashAddrDisabled] | auto[1] | auto[0] | 6726 | 1 | T61 | 71 | T58 | 49 | T38 | 43 | ||||
auto[1] | read | auto[SpiFlashAddrCfg] | auto[0] | auto[0] | 1422 | 1 | T24 | 1 | T85 | 1 | T217 | 1 | ||||
auto[1] | read | auto[SpiFlashAddrCfg] | auto[1] | auto[0] | 1346 | 1 | T24 | 3 | T61 | 19 | T57 | 2 | ||||
auto[1] | read | auto[SpiFlashAddr3b] | auto[0] | auto[0] | 1844 | 1 | T23 | 3 | T24 | 2 | T59 | 4 | ||||
auto[1] | read | auto[SpiFlashAddr3b] | auto[1] | auto[0] | 1616 | 1 | T24 | 1 | T61 | 9 | T57 | 1 | ||||
auto[1] | read | auto[SpiFlashAddr4b] | auto[0] | auto[0] | 1332 | 1 | T23 | 8 | T59 | 5 | T60 | 1 | ||||
auto[1] | read | auto[SpiFlashAddr4b] | auto[1] | auto[0] | 1302 | 1 | T24 | 3 | T61 | 24 | T57 | 1 | ||||
auto[1] | write | auto[SpiFlashAddrDisabled] | auto[0] | auto[0] | 119 | 1 | T61 | 1 | T58 | 2 | T38 | 2 | ||||
auto[1] | write | auto[SpiFlashAddrDisabled] | auto[0] | auto[1] | 100 | 1 | T106 | 1 | T53 | 3 | T113 | 1 | ||||
auto[1] | write | auto[SpiFlashAddrDisabled] | auto[1] | auto[0] | 89 | 1 | T106 | 1 | T218 | 4 | T102 | 1 | ||||
auto[1] | write | auto[SpiFlashAddrDisabled] | auto[1] | auto[1] | 102 | 1 | T57 | 1 | T106 | 1 | T129 | 4 | ||||
auto[1] | write | auto[SpiFlashAddrCfg] | auto[0] | auto[0] | 111 | 1 | T58 | 1 | T106 | 1 | T129 | 5 | ||||
auto[1] | write | auto[SpiFlashAddrCfg] | auto[0] | auto[1] | 121 | 1 | T58 | 1 | T38 | 3 | T53 | 2 | ||||
auto[1] | write | auto[SpiFlashAddrCfg] | auto[1] | auto[0] | 111 | 1 | T24 | 3 | T38 | 1 | T106 | 1 | ||||
auto[1] | write | auto[SpiFlashAddrCfg] | auto[1] | auto[1] | 74 | 1 | T61 | 1 | T58 | 1 | T38 | 2 | ||||
auto[1] | write | auto[SpiFlashAddr3b] | auto[0] | auto[0] | 117 | 1 | T61 | 2 | T38 | 2 | T126 | 1 | ||||
auto[1] | write | auto[SpiFlashAddr3b] | auto[0] | auto[1] | 85 | 1 | T38 | 1 | T133 | 1 | T53 | 1 | ||||
auto[1] | write | auto[SpiFlashAddr3b] | auto[1] | auto[0] | 83 | 1 | T61 | 2 | T58 | 1 | T106 | 2 | ||||
auto[1] | write | auto[SpiFlashAddr3b] | auto[1] | auto[1] | 114 | 1 | T24 | 2 | T57 | 1 | T58 | 1 | ||||
auto[1] | write | auto[SpiFlashAddr4b] | auto[0] | auto[0] | 133 | 1 | T61 | 1 | T58 | 4 | T38 | 2 | ||||
auto[1] | write | auto[SpiFlashAddr4b] | auto[0] | auto[1] | 89 | 1 | T104 | 5 | T126 | 3 | T133 | 2 | ||||
auto[1] | write | auto[SpiFlashAddr4b] | auto[1] | auto[0] | 93 | 1 | T58 | 1 | T38 | 1 | T106 | 1 | ||||
auto[1] | write | auto[SpiFlashAddr4b] | auto[1] | auto[1] | 71 | 1 | T38 | 1 | T113 | 1 | T219 | 2 |
NAME | COUNT | STATUS |
payload_swap_writes | 0 | Excluded |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 36 | 2 | 34 | 94.44 | 2 |
cp_is_flash | cp_dummy_cycles | cp_num_lanes | COUNT | AT LEAST | NUMBER | STATUS |
* | [values[1]] | [valids[0x0]] | -- | -- | 2 |
cp_is_flash | cp_dummy_cycles | cp_num_lanes | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | values[0] | valids[0x0] | 3860 | 1 | T15 | 2 | T25 | 18 | T110 | 10 | ||||
auto[0] | values[0] | valids[0x1] | 17631 | 1 | T4 | 2 | T16 | 35 | T22 | 4 | ||||
auto[0] | values[1] | valids[0x1] | 554 | 1 | T107 | 2 | T108 | 6 | T66 | 2 | ||||
auto[0] | values[2] | valids[0x0] | 570 | 1 | T63 | 2 | T208 | 2 | T66 | 5 | ||||
auto[0] | values[2] | valids[0x1] | 303 | 1 | T65 | 4 | T66 | 2 | T52 | 2 | ||||
auto[0] | values[3] | valids[0x0] | 527 | 1 | T67 | 2 | T51 | 2 | T66 | 2 | ||||
auto[0] | values[3] | valids[0x1] | 308 | 1 | T55 | 2 | T63 | 2 | T65 | 4 | ||||
auto[0] | values[4] | valids[0x0] | 532 | 1 | T83 | 2 | T209 | 4 | T66 | 1 | ||||
auto[0] | values[4] | valids[0x1] | 306 | 1 | T54 | 2 | T108 | 2 | T52 | 4 | ||||
auto[0] | values[5] | valids[0x0] | 527 | 1 | T22 | 4 | T209 | 6 | T211 | 4 | ||||
auto[0] | values[5] | valids[0x1] | 280 | 1 | T65 | 4 | T69 | 2 | T215 | 2 | ||||
auto[0] | values[6] | valids[0x0] | 528 | 1 | T62 | 2 | T204 | 2 | T220 | 2 | ||||
auto[0] | values[6] | valids[0x1] | 314 | 1 | T62 | 2 | T66 | 2 | T52 | 1 | ||||
auto[0] | values[7] | valids[0x0] | 495 | 1 | T107 | 2 | T108 | 4 | T66 | 6 | ||||
auto[0] | values[7] | valids[0x1] | 295 | 1 | T56 | 4 | T208 | 2 | T66 | 2 | ||||
auto[0] | values[8] | valids[0x0] | 3439 | 1 | T16 | 2 | T22 | 2 | T54 | 2 | ||||
auto[0] | values[8] | valids[0x1] | 2099 | 1 | T22 | 2 | T54 | 2 | T81 | 6 | ||||
auto[1] | values[0] | valids[0x0] | 3648 | 1 | T24 | 3 | T61 | 25 | T57 | 3 | ||||
auto[1] | values[0] | valids[0x1] | 14018 | 1 | T23 | 8 | T24 | 29 | T59 | 1 | ||||
auto[1] | values[1] | valids[0x1] | 484 | 1 | T61 | 2 | T58 | 3 | T38 | 1 | ||||
auto[1] | values[2] | valids[0x0] | 352 | 1 | T60 | 1 | T61 | 7 | T58 | 6 | ||||
auto[1] | values[2] | valids[0x1] | 228 | 1 | T58 | 4 | T126 | 2 | T106 | 6 | ||||
auto[1] | values[3] | valids[0x0] | 355 | 1 | T24 | 2 | T61 | 3 | T57 | 4 | ||||
auto[1] | values[3] | valids[0x1] | 223 | 1 | T61 | 1 | T57 | 1 | T58 | 4 | ||||
auto[1] | values[4] | valids[0x0] | 362 | 1 | T59 | 3 | T61 | 2 | T57 | 1 | ||||
auto[1] | values[4] | valids[0x1] | 253 | 1 | T24 | 1 | T61 | 2 | T58 | 6 | ||||
auto[1] | values[5] | valids[0x0] | 357 | 1 | T61 | 2 | T58 | 6 | T38 | 1 | ||||
auto[1] | values[5] | valids[0x1] | 208 | 1 | T61 | 6 | T58 | 2 | T38 | 5 | ||||
auto[1] | values[6] | valids[0x0] | 317 | 1 | T59 | 4 | T61 | 3 | T58 | 4 | ||||
auto[1] | values[6] | valids[0x1] | 236 | 1 | T24 | 1 | T217 | 1 | T61 | 3 | ||||
auto[1] | values[7] | valids[0x0] | 362 | 1 | T61 | 3 | T38 | 2 | T126 | 1 | ||||
auto[1] | values[7] | valids[0x1] | 210 | 1 | T61 | 1 | T57 | 1 | T58 | 6 | ||||
auto[1] | values[8] | valids[0x0] | 2365 | 1 | T23 | 3 | T24 | 2 | T85 | 1 | ||||
auto[1] | values[8] | valids[0x1] | 1578 | 1 | T24 | 2 | T59 | 1 | T217 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |