Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3285642

1

T4

1808

T15

159

T16

269

auto[1]

27554

1

T16

27

T24

20

T66

8

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

951391

1

T4

1296

T15

159

T16

5

auto[1]

2361805

1

T4

512

T16

291

T24

815

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	668775	1			T4	375		T15	10		T16	296
auto[524288:1048575]	382538	1			T4	1		T15	64		T22	36
auto[1048576:1572863]	381377	1			T4	1367		T20	1		T22	35
auto[1572864:2097151]	294993	1			T22	14		T25	6		T59	185
auto[2097152:2621439]	463055	1			T23	129		T25	1		T63	70
auto[2621440:3145727]	344157	1			T15	80		T20	1		T22	39
auto[3145728:3670015]	376776	1			T4	1		T21	3		T22	45
auto[3670016:4194303]	401525	1			T4	64		T15	5		T21	1

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2392918

1

T4

519

T15

34

T16

295

auto[1]

920278

1

T4

1289

T15

125

T16

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2882012

1

T4

1808

T15

159

T16

296

auto[1]

431184

1

T25

10

T110

33

T66

1338

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	232164	1			T4	117		T15	10		T16	3
auto[0]	auto[0]	auto[0:524287]	auto[1]	370429	1			T4	258		T16	266		T24	535
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	104806	1			T4	1		T15	64		T22	36
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	230373	1			T24	5		T211	137		T66	640
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	122217	1			T4	1113		T20	1		T22	35
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	208839	1			T4	254		T66	10		T61	1669
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	67504	1			T22	14		T25	6		T59	185
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	175556	1			T211	244		T61	5		T58	384
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	104128	1			T23	129		T25	1		T63	70
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	277367	1			T211	50		T61	514		T52	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	100964	1			T15	80		T20	1		T22	39
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	217063	1			T211	46		T66	256		T52	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	105370	1			T4	1		T21	3		T22	45
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	215730	1			T61	2		T58	517		T74	865
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	103704	1			T4	64		T15	5		T21	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	223283	1			T24	258		T211	137		T58	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	1143	1			T25	7		T66	9		T52	21
auto[0]	auto[1]	auto[0:524287]	auto[1]	59710	1			T53	1		T113	257		T245	2
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	748	1			T25	3		T66	42		T111	6
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	42480	1			T66	899		T58	256		T38	257
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	556	1			T61	2		T57	1		T58	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	46757	1			T61	133		T57	1		T58	257
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	905	1			T110	12		T61	1		T57	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	47803	1			T57	256		T58	1		T38	1025
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1064	1			T61	1		T57	2		T58	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	77747	1			T58	256		T76	2485		T53	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1102	1			T110	11		T52	2		T58	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	22476	1			T38	1		T106	4		T113	518
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	737	1			T110	5		T52	21		T58	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	51651	1			T52	2768		T104	4		T76	2267
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	645	1			T110	5		T66	19		T52	8
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	70621	1			T66	369		T52	715		T58	105
auto[1]	auto[0]	auto[0:524287]	auto[0]	568	1			T16	2		T66	6		T61	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	4237	1			T16	25		T61	14		T57	20
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	384	1			T24	1		T58	1		T38	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3183	1			T24	4		T58	31		T38	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	311	1			T61	1		T38	1		T76	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2395	1			T61	8		T38	3		T76	51
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	409	1			T66	2		T38	2		T126	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2133	1			T38	3		T126	3		T76	134
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	347	1			T61	1		T76	3		T106	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1667	1			T61	1		T76	48		T106	16
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	321	1			T38	1		T133	5		T53	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1802	1			T38	14		T53	67		T79	8
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	373	1			T61	2		T58	1		T104	9
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2132	1			T61	32		T58	11		T126	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	328	1			T24	2		T58	1		T106	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1925	1			T24	13		T58	2		T106	76
auto[1]	auto[1]	auto[0:524287]	auto[0]	69	1			T52	3		T53	1		T113	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	455	1			T53	18		T245	53		T89	6
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	54	1			T38	1		T106	2		T113	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	510	1			T38	1		T106	56		T282	14
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	57	1			T57	1		T58	1		T77	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	245	1			T57	17		T58	13		T77	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	91	1			T58	1		T38	1		T77	5
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	592	1			T58	29		T38	9		T53	7
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	94	1			T53	1		T79	5		T114	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	641	1			T53	37		T114	52		T193	17
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	89	1			T38	1		T113	1		T207	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	340	1			T38	2		T113	32		T207	5
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	61	1			T53	1		T212	1		T213	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	722	1			T53	8		T212	1		T213	21
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	78	1			T52	5		T105	1		T77	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	941	1			T52	146		T105	14		T270	27

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1942072	1			T4	519		T15	34		T16	268
auto[0]	auto[0]	auto[1]	917425	1			T4	1289		T15	125		T16	1
auto[0]	auto[1]	auto[0]	423893	1			T25	10		T110	9		T66	1338
auto[0]	auto[1]	auto[1]	2252	1			T110	24		T111	3		T58	1
auto[1]	auto[0]	auto[0]	22023	1			T16	27		T24	20		T66	6
auto[1]	auto[0]	auto[1]	492	1			T66	2		T61	1		T57	1
auto[1]	auto[1]	auto[0]	4930	1			T57	17		T52	152		T58	44
auto[1]	auto[1]	auto[1]	109	1			T57	1		T52	2		T77	3