Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2472849	1			T1	1		T2	1		T4	1
all_pins[1]	2472849	1			T1	1		T2	1		T4	1
all_pins[2]	2472849	1			T1	1		T2	1		T4	1
all_pins[3]	2472849	1			T1	1		T2	1		T4	1
all_pins[4]	2472849	1			T1	1		T2	1		T4	1
all_pins[5]	2472849	1			T1	1		T2	1		T4	1
all_pins[6]	2472849	1			T1	1		T2	1		T4	1
all_pins[7]	2472849	1			T1	1		T2	1		T4	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19647872	1			T1	8		T2	8		T4	8
values[0x1]	134920	1			T33	26		T35	11		T36	17
transitions[0x0=>0x1]	133829	1			T33	20		T35	11		T36	9
transitions[0x1=>0x0]	133845	1			T33	20		T35	11		T36	9

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2471894	1			T1	1		T2	1		T4	1
all_pins[0]	values[0x1]	955	1			T33	5		T36	4		T37	7
all_pins[0]	transitions[0x0=>0x1]	809	1			T33	5		T36	2		T37	5
all_pins[0]	transitions[0x1=>0x0]	488	1			T33	3		T35	1		T126	1
all_pins[1]	values[0x0]	2472215	1			T1	1		T2	1		T4	1
all_pins[1]	values[0x1]	634	1			T33	3		T35	1		T36	2
all_pins[1]	transitions[0x0=>0x1]	586	1			T33	2		T35	1		T36	1
all_pins[1]	transitions[0x1=>0x0]	158	1			T33	4		T35	2		T36	4
all_pins[2]	values[0x0]	2472643	1			T1	1		T2	1		T4	1
all_pins[2]	values[0x1]	206	1			T33	5		T35	2		T36	5
all_pins[2]	transitions[0x0=>0x1]	163	1			T33	3		T35	2		T36	2
all_pins[2]	transitions[0x1=>0x0]	162	1			T33	2		T35	2		T37	8
all_pins[3]	values[0x0]	2472644	1			T1	1		T2	1		T4	1
all_pins[3]	values[0x1]	205	1			T33	4		T35	2		T36	3
all_pins[3]	transitions[0x0=>0x1]	159	1			T33	3		T35	2		T36	3
all_pins[3]	transitions[0x1=>0x0]	154	1			T33	3		T35	1		T37	4
all_pins[4]	values[0x0]	2472649	1			T1	1		T2	1		T4	1
all_pins[4]	values[0x1]	200	1			T33	4		T35	1		T37	7
all_pins[4]	transitions[0x0=>0x1]	153	1			T33	2		T35	1		T37	7
all_pins[4]	transitions[0x1=>0x0]	1505	1			T35	3		T36	1		T37	2
all_pins[5]	values[0x0]	2471297	1			T1	1		T2	1		T4	1
all_pins[5]	values[0x1]	1552	1			T33	2		T35	3		T36	1
all_pins[5]	transitions[0x0=>0x1]	875	1			T33	2		T35	3		T36	1
all_pins[5]	transitions[0x1=>0x0]	130336	1			T33	3		T35	1		T37	7
all_pins[6]	values[0x0]	2341836	1			T1	1		T2	1		T4	1
all_pins[6]	values[0x1]	131013	1			T33	3		T35	1		T37	7
all_pins[6]	transitions[0x0=>0x1]	130979	1			T33	3		T35	1		T37	6
all_pins[6]	transitions[0x1=>0x0]	121	1			T35	1		T36	2		T37	4
all_pins[7]	values[0x0]	2472694	1			T1	1		T2	1		T4	1
all_pins[7]	values[0x1]	155	1			T35	1		T36	2		T37	5
all_pins[7]	transitions[0x0=>0x1]	105	1			T35	1		T37	3		T126	1
all_pins[7]	transitions[0x1=>0x0]	921	1			T33	5		T36	2		T37	5