Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18880

1

T4

2

T15

2

T16

37

auto[1]

13688

1

T55

10

T56

12

T70

4

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4188	1			T81	12		T201	10		T71	4
values[1]	4878	1			T25	18		T70	4		T111	14
values[2]	3358	1			T62	12		T83	24		T209	20
values[3]	4461	1			T22	12		T214	12		T76	117
values[4]	3990	1			T55	10		T63	6		T67	6
values[5]	3545	1			T4	2		T15	2		T211	18
values[6]	4197	1			T16	37		T56	12		T65	16
values[7]	3951	1			T54	10		T110	10		T131	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3932	1			T70	4		T201	10		T68	8
values[1]	4115	1			T131	6		T306	2		T307	2
values[2]	4328	1			T54	10		T55	10		T56	12
values[3]	3734	1			T25	18		T64	6		T66	20
values[4]	4266	1			T107	4		T66	20		T52	20
values[5]	4020	1			T16	37		T51	8		T111	14
values[6]	3819	1			T4	2		T22	12		T67	6
values[7]	4354	1			T15	2		T63	6		T83	24

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	338	1			T201	10		T286	12		T78	13
auto[0]	values[0]	values[1]	238	1			T307	2		T308	4		T89	32
auto[0]	values[0]	values[2]	380	1			T81	12		T90	12		T247	14
auto[0]	values[0]	values[3]	376	1			T256	54		T309	16		T300	9
auto[0]	values[0]	values[4]	241	1			T310	4		T90	12		T193	12
auto[0]	values[0]	values[5]	202	1			T249	8		T90	13		T193	29
auto[0]	values[0]	values[6]	287	1			T213	7		T89	10		T241	114
auto[0]	values[0]	values[7]	186	1			T311	2		T79	11		T263	13
auto[0]	values[1]	values[0]	445	1			T68	8		T76	74		T312	23
auto[0]	values[1]	values[1]	362	1			T52	11		T74	34		T313	64
auto[0]	values[1]	values[2]	479	1			T76	12		T314	2		T256	48
auto[0]	values[1]	values[3]	441	1			T25	18		T213	71		T271	12
auto[0]	values[1]	values[4]	213	1			T52	6		T69	16		T105	16
auto[0]	values[1]	values[5]	568	1			T111	14		T297	18		T315	22
auto[0]	values[1]	values[6]	351	1			T259	46		T193	8		T256	12
auto[0]	values[1]	values[7]	338	1			T300	14		T280	42		T316	24
auto[0]	values[2]	values[0]	216	1			T72	20		T76	39		T78	13
auto[0]	values[2]	values[1]	203	1			T317	4		T318	16		T247	69
auto[0]	values[2]	values[2]	186	1			T62	12		T79	11		T196	8
auto[0]	values[2]	values[3]	196	1			T66	10		T212	15		T89	11
auto[0]	values[2]	values[4]	292	1			T107	4		T305	4		T319	2
auto[0]	values[2]	values[5]	184	1			T320	16		T89	30		T240	11
auto[0]	values[2]	values[6]	180	1			T209	20		T108	14		T216	9
auto[0]	values[2]	values[7]	372	1			T83	24		T66	12		T321	2
auto[0]	values[3]	values[0]	403	1			T76	14		T213	80		T262	11
auto[0]	values[3]	values[1]	484	1			T76	13		T105	6		T322	4
auto[0]	values[3]	values[2]	370	1			T214	12		T89	14		T216	17
auto[0]	values[3]	values[3]	204	1			T269	20		T323	4		T130	10
auto[0]	values[3]	values[4]	328	1			T297	12		T324	31		T240	12
auto[0]	values[3]	values[5]	332	1			T212	19		T325	4		T256	22
auto[0]	values[3]	values[6]	190	1			T22	12		T262	9		T193	13
auto[0]	values[3]	values[7]	276	1			T326	8		T262	11		T247	13
auto[0]	values[4]	values[0]	273	1			T76	10		T213	15		T295	11
auto[0]	values[4]	values[1]	128	1			T327	22		T216	8		T300	15
auto[0]	values[4]	values[2]	298	1			T210	4		T302	12		T77	9
auto[0]	values[4]	values[3]	252	1			T64	6		T293	19		T328	4
auto[0]	values[4]	values[4]	153	1			T205	15		T329	4		T96	2
auto[0]	values[4]	values[5]	354	1			T51	8		T330	4		T234	15
auto[0]	values[4]	values[6]	317	1			T67	6		T208	18		T262	11
auto[0]	values[4]	values[7]	530	1			T63	6		T331	6		T256	14
auto[0]	values[5]	values[0]	325	1			T193	22		T250	16		T266	26
auto[0]	values[5]	values[1]	568	1			T278	16		T76	125		T89	18
auto[0]	values[5]	values[2]	275	1			T52	12		T255	10		T332	14
auto[0]	values[5]	values[3]	102	1			T205	14		T293	20		T235	14
auto[0]	values[5]	values[4]	180	1			T193	14		T256	38		T130	10
auto[0]	values[5]	values[5]	146	1			T256	13		T300	9		T297	21
auto[0]	values[5]	values[6]	370	1			T4	2		T211	18		T66	12
auto[0]	values[5]	values[7]	322	1			T15	2		T292	8		T333	2
auto[0]	values[6]	values[0]	188	1			T303	24		T216	10		T304	13
auto[0]	values[6]	values[1]	284	1			T299	40		T256	7		T267	9
auto[0]	values[6]	values[2]	165	1			T232	4		T334	22		T335	4
auto[0]	values[6]	values[3]	376	1			T277	2		T76	5		T90	15
auto[0]	values[6]	values[4]	458	1			T66	14		T205	11		T336	6
auto[0]	values[6]	values[5]	225	1			T16	37		T212	12		T276	14
auto[0]	values[6]	values[6]	292	1			T66	15		T109	8		T76	11
auto[0]	values[6]	values[7]	298	1			T105	58		T73	10		T89	10
auto[0]	values[7]	values[0]	216	1			T215	16		T89	8		T216	12
auto[0]	values[7]	values[1]	195	1			T131	6		T337	6		T128	18
auto[0]	values[7]	values[2]	384	1			T54	10		T233	18		T216	12
auto[0]	values[7]	values[3]	277	1			T79	7		T89	15		T295	9
auto[0]	values[7]	values[4]	312	1			T77	12		T244	22		T283	22
auto[0]	values[7]	values[5]	310	1			T220	14		T338	8		T339	4
auto[0]	values[7]	values[6]	230	1			T293	6		T340	15		T341	10
auto[0]	values[7]	values[7]	216	1			T110	10		T198	2		T216	16
auto[1]	values[0]	values[0]	216	1			T78	9		T216	8		T193	12
auto[1]	values[0]	values[1]	244	1			T89	11		T263	5		T239	4
auto[1]	values[0]	values[2]	358	1			T80	22		T90	8		T247	6
auto[1]	values[0]	values[3]	333	1			T256	7		T300	11		T271	7
auto[1]	values[0]	values[4]	179	1			T90	10		T193	8		T304	21
auto[1]	values[0]	values[5]	213	1			T90	20		T193	5		T265	55
auto[1]	values[0]	values[6]	202	1			T213	67		T89	10		T241	12
auto[1]	values[0]	values[7]	195	1			T71	4		T79	9		T342	10
auto[1]	values[1]	values[0]	117	1			T70	4		T76	9		T193	6
auto[1]	values[1]	values[1]	247	1			T52	9		T74	5		T256	11
auto[1]	values[1]	values[2]	425	1			T76	11		T256	11		T280	12
auto[1]	values[1]	values[3]	153	1			T213	5		T271	8		T343	10
auto[1]	values[1]	values[4]	125	1			T52	14		T105	20		T193	8
auto[1]	values[1]	values[5]	143	1			T297	9		T315	18		T240	11
auto[1]	values[1]	values[6]	234	1			T75	22		T193	27		T256	20
auto[1]	values[1]	values[7]	237	1			T300	6		T280	11		T324	31
auto[1]	values[2]	values[0]	157	1			T76	11		T78	11		T344	8
auto[1]	values[2]	values[1]	121	1			T247	8		T263	11		T266	20
auto[1]	values[2]	values[2]	117	1			T79	9		T196	15		T345	4
auto[1]	values[2]	values[3]	187	1			T66	10		T212	10		T89	22
auto[1]	values[2]	values[4]	200	1			T258	3		T44	18		T346	13
auto[1]	values[2]	values[5]	286	1			T89	15		T240	181		T44	12
auto[1]	values[2]	values[6]	166	1			T216	11		T193	33		T266	18
auto[1]	values[2]	values[7]	295	1			T66	8		T205	10		T263	8
auto[1]	values[3]	values[0]	218	1			T76	6		T213	12		T262	10
auto[1]	values[3]	values[1]	271	1			T76	84		T105	14		T238	8
auto[1]	values[3]	values[2]	225	1			T347	6		T89	6		T216	23
auto[1]	values[3]	values[3]	223	1			T130	10		T264	10		T271	5
auto[1]	values[3]	values[4]	199	1			T297	8		T324	6		T240	29
auto[1]	values[3]	values[5]	235	1			T212	6		T256	39		T348	4
auto[1]	values[3]	values[6]	162	1			T262	54		T193	7		T239	8
auto[1]	values[3]	values[7]	341	1			T99	22		T262	49		T247	7
auto[1]	values[4]	values[0]	146	1			T76	10		T213	5		T295	9
auto[1]	values[4]	values[1]	156	1			T216	12		T300	8		T271	15
auto[1]	values[4]	values[2]	138	1			T55	10		T77	11		T130	14
auto[1]	values[4]	values[3]	143	1			T293	8		T130	9		T265	4
auto[1]	values[4]	values[4]	289	1			T205	5		T247	29		T349	15
auto[1]	values[4]	values[5]	345	1			T234	5		T267	9		T130	10
auto[1]	values[4]	values[6]	312	1			T262	9		T256	8		T304	9
auto[1]	values[4]	values[7]	156	1			T243	16		T256	8		T247	15
auto[1]	values[5]	values[0]	190	1			T193	9		T266	9		T267	6
auto[1]	values[5]	values[1]	167	1			T76	10		T89	2		T246	12
auto[1]	values[5]	values[2]	115	1			T204	12		T52	8		T304	25
auto[1]	values[5]	values[3]	50	1			T205	6		T293	10		T350	5
auto[1]	values[5]	values[4]	233	1			T193	26		T256	6		T130	10
auto[1]	values[5]	values[5]	126	1			T256	40		T300	11		T297	8
auto[1]	values[5]	values[6]	119	1			T66	8		T213	8		T266	6
auto[1]	values[5]	values[7]	257	1			T304	31		T264	11		T265	12
auto[1]	values[6]	values[0]	116	1			T284	2		T216	10		T304	7
auto[1]	values[6]	values[1]	209	1			T306	2		T256	23		T267	11
auto[1]	values[6]	values[2]	195	1			T56	12		T351	8		T300	10
auto[1]	values[6]	values[3]	278	1			T76	38		T90	8		T352	20
auto[1]	values[6]	values[4]	469	1			T66	6		T205	9		T300	41
auto[1]	values[6]	values[5]	198	1			T212	8		T266	7		T130	6
auto[1]	values[6]	values[6]	229	1			T66	5		T76	9		T350	44
auto[1]	values[6]	values[7]	217	1			T65	16		T105	4		T89	10
auto[1]	values[7]	values[0]	368	1			T89	20		T216	8		T262	75
auto[1]	values[7]	values[1]	238	1			T262	7		T247	13		T280	22
auto[1]	values[7]	values[2]	218	1			T216	8		T295	7		T247	5
auto[1]	values[7]	values[3]	143	1			T79	13		T89	5		T295	11
auto[1]	values[7]	values[4]	395	1			T77	8		T90	8		T246	12
auto[1]	values[7]	values[5]	153	1			T253	5		T353	12		T44	5
auto[1]	values[7]	values[6]	178	1			T293	17		T340	5		T354	7
auto[1]	values[7]	values[7]	118	1			T216	4		T247	10		T315	9