Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	371	1			T211	10		T66	2		T278	2
auto[ReadAddrCrossIntoMailbox]	265	1			T66	3		T74	1		T76	1
auto[ReadAddrCrossOutOfMailbox]	340	1			T51	4		T107	4		T66	1
auto[ReadAddrCrossAllMailbox]	219	1			T51	2		T277	2		T286	2
auto[ReadAddrOutsideMailbox]	3561	1			T22	6		T54	2		T55	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2331

1

T22

3

T54

1

T55

2

auto[1]

2425

1

T22

3

T54

1

T55

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	757	1			T55	2		T81	4		T51	4
read_ops[0x0b]	801	1			T208	2		T108	6		T66	2
read_ops[0x3b]	809	1			T208	2		T107	2		T211	6
read_ops[0x6b]	813	1			T22	2		T56	2		T62	2
read_ops[0xbb]	774	1			T56	4		T63	2		T81	2
read_ops[0xeb]	802	1			T22	4		T54	2		T55	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T76	1		T303	1		T216	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T66	2		T303	1		T262	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T281	1		T303	1		T350	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T281	1		T303	1		T304	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T51	1		T107	1		T76	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T51	1		T107	1		T293	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T277	1		T76	1		T105	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T277	1		T293	1		T262	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T55	1		T81	2		T51	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T55	1		T81	2		T51	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T288	2		T350	1		T130	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T77	1		T213	1		T89	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T76	1		T293	1		T216	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T262	2		T256	1		T330	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T303	1		T262	1		T295	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T66	1		T76	1		T303	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T286	1		T303	1		T256	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T286	1		T303	1		T89	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	294	1			T208	1		T108	3		T66	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T208	1		T108	3		T204	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T211	2		T305	1		T216	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T211	2		T305	1		T77	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T66	2		T303	1		T246	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T293	1		T303	1		T216	3
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T107	1		T310	1		T281	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T107	1		T77	1		T310	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T281	1		T303	1		T262	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T281	1		T303	1		T262	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	297	1			T208	1		T211	1		T108	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T208	1		T211	1		T108	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T211	2		T213	1		T262	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T211	2		T216	1		T296	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	13	1			T216	1		T304	2		T263	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T90	1		T193	1		T247	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T77	1		T89	1		T216	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T90	2		T256	1		T300	3
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T51	1		T303	2		T348	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T51	1		T303	2		T262	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	312	1			T22	1		T56	1		T62	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T22	1		T56	1		T62	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T211	1		T278	1		T213	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T211	1		T278	1		T105	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T293	1		T216	2		T350	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T74	1		T105	1		T193	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	37	1			T76	2		T310	1		T213	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T310	1		T90	2		T193	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T216	1		T262	1		T193	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T216	1		T239	1		T357	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	252	1			T56	2		T63	1		T81	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	310	1			T56	2		T63	1		T81	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T305	1		T255	2		T293	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T305	1		T76	1		T78	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T205	2		T193	1		T350	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T66	1		T304	1		T343	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T51	1		T303	1		T216	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T51	1		T76	2		T213	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T105	1		T303	1		T300	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T77	1		T303	1		T271	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	317	1			T22	2		T54	1		T55	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	283	1			T22	2		T54	1		T55	1