Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4009	1			T65	16		T110	10		T210	4
values[1]	3967	1			T15	2		T67	6		T64	6
values[2]	4634	1			T25	18		T62	12		T72	20
values[3]	5025	1			T16	37		T70	4		T211	18
values[4]	3191	1			T56	12		T51	8		T232	4
values[5]	3795	1			T81	12		T208	18		T209	20
values[6]	3523	1			T63	6		T131	6		T107	4
values[7]	4424	1			T4	2		T22	12		T54	10

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4222	1			T22	12		T54	10		T55	10
values[1]	3664	1			T81	12		T52	20		T109	8
values[2]	4057	1			T15	2		T16	37		T208	18
values[3]	4753	1			T209	20		T51	8		T66	40
values[4]	3954	1			T56	12		T65	16		T108	14
values[5]	4210	1			T4	2		T67	6		T64	6
values[6]	3765	1			T25	18		T63	6		T74	39
values[7]	3943	1			T83	24		T131	6		T232	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31786

1

T4

2

T15

2

T16

37

auto[1]

782

1

T55

2

T66

3

T71

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	700	1			T68	8		T326	8		T283	22
auto[0]	values[0]	values[1]	277	1			T327	22		T351	8		T193	20
auto[0]	values[0]	values[2]	434	1			T210	4		T79	20		T216	19
auto[0]	values[0]	values[3]	595	1			T251	24		T358	6		T300	20
auto[0]	values[0]	values[4]	400	1			T65	16		T329	4		T320	16
auto[0]	values[0]	values[5]	621	1			T110	10		T89	28		T193	44
auto[0]	values[0]	values[6]	408	1			T239	20		T316	24		T258	102
auto[0]	values[0]	values[7]	479	1			T302	12		T212	22		T246	32
auto[0]	values[1]	values[0]	395	1			T89	42		T90	20		T193	18
auto[0]	values[1]	values[1]	462	1			T79	18		T89	40		T318	16
auto[0]	values[1]	values[2]	473	1			T15	2		T216	20		T258	27
auto[0]	values[1]	values[3]	754	1			T66	20		T331	6		T347	6
auto[0]	values[1]	values[4]	277	1			T66	20		T193	20		T328	4
auto[0]	values[1]	values[5]	400	1			T67	6		T64	6		T214	12
auto[0]	values[1]	values[6]	390	1			T314	2		T285	76		T130	20
auto[0]	values[1]	values[7]	736	1			T71	2		T336	6		T359	14
auto[0]	values[2]	values[0]	461	1			T62	12		T76	20		T295	19
auto[0]	values[2]	values[1]	741	1			T255	10		T293	23		T193	43
auto[0]	values[2]	values[2]	842	1			T259	46		T79	20		T350	21
auto[0]	values[2]	values[3]	708	1			T72	20		T76	79		T78	21
auto[0]	values[2]	values[4]	530	1			T76	185		T308	4		T360	4
auto[0]	values[2]	values[5]	397	1			T313	64		T96	2		T295	20
auto[0]	values[2]	values[6]	365	1			T25	18		T90	23		T300	22
auto[0]	values[2]	values[7]	487	1			T90	31		T348	18		T335	4
auto[0]	values[3]	values[0]	860	1			T70	4		T198	2		T105	62
auto[0]	values[3]	values[1]	491	1			T215	16		T76	23		T361	10
auto[0]	values[3]	values[2]	787	1			T16	37		T211	18		T90	28
auto[0]	values[3]	values[3]	591	1			T304	21		T300	20		T130	20
auto[0]	values[3]	values[4]	521	1			T111	14		T78	23		T80	18
auto[0]	values[3]	values[5]	747	1			T66	19		T205	20		T311	2
auto[0]	values[3]	values[6]	545	1			T76	18		T244	22		T295	17
auto[0]	values[3]	values[7]	368	1			T76	20		T262	39		T362	20
auto[0]	values[4]	values[0]	547	1			T256	40		T363	20		T260	12
auto[0]	values[4]	values[1]	267	1			T109	8		T89	20		T262	63
auto[0]	values[4]	values[2]	328	1			T293	27		T239	20		T267	20
auto[0]	values[4]	values[3]	421	1			T51	8		T77	18		T269	20
auto[0]	values[4]	values[4]	271	1			T56	12		T284	2		T276	14
auto[0]	values[4]	values[5]	552	1			T52	38		T89	20		T90	20
auto[0]	values[4]	values[6]	514	1			T105	35		T304	41		T364	4
auto[0]	values[4]	values[7]	234	1			T232	4		T69	16		T322	4
auto[0]	values[5]	values[0]	343	1			T310	4		T212	20		T216	19
auto[0]	values[5]	values[1]	474	1			T81	12		T52	20		T263	20
auto[0]	values[5]	values[2]	387	1			T208	18		T201	10		T321	2
auto[0]	values[5]	values[3]	534	1			T209	20		T66	20		T220	14
auto[0]	values[5]	values[4]	578	1			T278	16		T73	10		T256	61
auto[0]	values[5]	values[5]	462	1			T306	2		T233	18		T265	20
auto[0]	values[5]	values[6]	502	1			T75	16		T213	73		T365	10
auto[0]	values[5]	values[7]	406	1			T305	4		T212	24		T216	20
auto[0]	values[6]	values[0]	248	1			T77	20		T205	20		T243	16
auto[0]	values[6]	values[1]	467	1			T193	41		T256	83		T274	24
auto[0]	values[6]	values[2]	265	1			T105	20		T256	32		T349	20
auto[0]	values[6]	values[3]	581	1			T277	2		T332	14		T304	25
auto[0]	values[6]	values[4]	533	1			T213	74		T89	33		T99	20
auto[0]	values[6]	values[5]	483	1			T107	4		T66	18		T204	12
auto[0]	values[6]	values[6]	410	1			T63	6		T128	18		T213	19
auto[0]	values[6]	values[7]	458	1			T131	6		T333	2		T352	16
auto[0]	values[7]	values[0]	575	1			T22	12		T54	10		T55	8
auto[0]	values[7]	values[1]	400	1			T299	40		T366	18		T240	20
auto[0]	values[7]	values[2]	447	1			T307	2		T281	10		T247	21
auto[0]	values[7]	values[3]	467	1			T342	8		T367	6		T247	25
auto[0]	values[7]	values[4]	751	1			T108	14		T337	6		T89	25
auto[0]	values[7]	values[5]	420	1			T4	2		T213	20		T317	4
auto[0]	values[7]	values[6]	549	1			T74	37		T286	12		T238	8
auto[0]	values[7]	values[7]	670	1			T83	24		T76	96		T205	20
auto[1]	values[0]	values[0]	8	1			T246	1		T271	2		T368	1
auto[1]	values[0]	values[1]	5	1			T369	1		T370	2		T371	2
auto[1]	values[0]	values[2]	14	1			T216	1		T372	2		T373	4
auto[1]	values[0]	values[3]	15	1			T265	5		T374	1		T253	1
auto[1]	values[0]	values[4]	13	1			T193	2		T263	2		T375	2
auto[1]	values[0]	values[5]	14	1			T193	5		T130	1		T240	4
auto[1]	values[0]	values[6]	6	1			T353	1		T376	1		T377	3
auto[1]	values[0]	values[7]	20	1			T212	3		T246	1		T240	4
auto[1]	values[1]	values[0]	5	1			T89	1		T193	2		T354	1
auto[1]	values[1]	values[1]	14	1			T79	2		T240	1		T369	3
auto[1]	values[1]	values[2]	12	1			T258	1		T374	1		T273	2
auto[1]	values[1]	values[3]	14	1			T247	1		T271	5		T343	2
auto[1]	values[1]	values[4]	2	1			T378	2		-	-		-	-
auto[1]	values[1]	values[5]	16	1			T315	1		T374	1		T253	3
auto[1]	values[1]	values[6]	2	1			T167	2		-	-		-	-
auto[1]	values[1]	values[7]	15	1			T71	2		T370	2		T346	2
auto[1]	values[2]	values[0]	8	1			T295	1		T264	2		T44	1
auto[1]	values[2]	values[1]	16	1			T240	5		T379	2		T176	2
auto[1]	values[2]	values[2]	24	1			T350	5		T130	3		T271	1
auto[1]	values[2]	values[3]	11	1			T76	4		T78	1		T267	2
auto[1]	values[2]	values[4]	9	1			T315	2		T368	1		T380	2
auto[1]	values[2]	values[5]	8	1			T295	1		T381	1		T382	4
auto[1]	values[2]	values[6]	9	1			T300	2		T383	3		T384	2
auto[1]	values[2]	values[7]	18	1			T90	2		T348	7		T385	6
auto[1]	values[3]	values[0]	18	1			T304	2		T265	2		T343	6
auto[1]	values[3]	values[1]	24	1			T344	4		T247	5		T354	4
auto[1]	values[3]	values[2]	12	1			T90	1		T262	1		T385	4
auto[1]	values[3]	values[3]	16	1			T304	1		T354	3		T386	1
auto[1]	values[3]	values[4]	13	1			T78	1		T80	4		T380	1
auto[1]	values[3]	values[5]	11	1			T66	1		T165	3		T44	2
auto[1]	values[3]	values[6]	18	1			T76	2		T295	3		T130	1
auto[1]	values[3]	values[7]	3	1			T262	2		T376	1		-	-
auto[1]	values[4]	values[0]	7	1			T256	1		T300	1		T44	1
auto[1]	values[4]	values[1]	7	1			T263	1		T370	4		T383	2
auto[1]	values[4]	values[2]	2	1			T387	2		-	-		-	-
auto[1]	values[4]	values[3]	6	1			T77	2		T267	1		T379	1
auto[1]	values[4]	values[4]	9	1			T196	1		T386	2		T388	1
auto[1]	values[4]	values[5]	17	1			T52	2		T90	2		T256	3
auto[1]	values[4]	values[6]	4	1			T105	1		T178	1		T389	2
auto[1]	values[4]	values[7]	5	1			T304	1		T271	2		T390	2
auto[1]	values[5]	values[0]	17	1			T216	1		T354	1		T253	1
auto[1]	values[5]	values[1]	8	1			T315	3		T253	1		T346	3
auto[1]	values[5]	values[2]	11	1			T247	1		T266	2		T345	3
auto[1]	values[5]	values[3]	11	1			T304	2		T300	3		T130	2
auto[1]	values[5]	values[4]	8	1			T354	1		T275	1		T44	1
auto[1]	values[5]	values[5]	22	1			T324	3		T345	2		T167	2
auto[1]	values[5]	values[6]	19	1			T75	6		T213	1		T247	5
auto[1]	values[5]	values[7]	13	1			T212	1		T262	1		T304	1
auto[1]	values[6]	values[0]	5	1			T374	2		T391	2		T392	1
auto[1]	values[6]	values[1]	4	1			T193	1		T239	1		T354	1
auto[1]	values[6]	values[2]	5	1			T393	1		T394	2		T179	2
auto[1]	values[6]	values[3]	10	1			T304	4		T266	2		T130	1
auto[1]	values[6]	values[4]	15	1			T213	2		T99	2		T254	2
auto[1]	values[6]	values[5]	19	1			T66	2		T265	5		T287	3
auto[1]	values[6]	values[6]	7	1			T213	1		T265	1		T287	1
auto[1]	values[6]	values[7]	13	1			T352	4		T395	3		T178	2
auto[1]	values[7]	values[0]	25	1			T55	2		T213	2		T300	4
auto[1]	values[7]	values[1]	7	1			T385	1		T165	4		T388	2
auto[1]	values[7]	values[2]	14	1			T247	1		T263	4		T253	1
auto[1]	values[7]	values[3]	19	1			T342	2		T247	3		T280	2
auto[1]	values[7]	values[4]	24	1			T271	3		T297	1		T240	6
auto[1]	values[7]	values[5]	21	1			T315	2		T253	2		T379	2
auto[1]	values[7]	values[6]	17	1			T74	2		T265	3		T253	2
auto[1]	values[7]	values[7]	18	1			T76	1		T256	1		T258	4