Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	778	1			T33	17		T35	7		T36	7
all_values[1]	778	1			T33	17		T35	7		T36	7
all_values[2]	778	1			T33	17		T35	7		T36	7
all_values[3]	778	1			T33	17		T35	7		T36	7
all_values[4]	778	1			T33	17		T35	7		T36	7
all_values[5]	778	1			T33	17		T35	7		T36	7
all_values[6]	778	1			T33	17		T35	7		T36	7
all_values[7]	778	1			T33	17		T35	7		T36	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3271

1

T33

84

T35

28

T36

32

auto[1]

2953

1

T33

52

T35

28

T36

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2480

1

T33

62

T35

29

T36

20

auto[1]

3744

1

T33

74

T35

27

T36

36

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3554

1

T33

84

T35

30

T36

33

auto[1]

2670

1

T33

52

T35

26

T36

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	157	1			T33	5		T35	2		T36	2
all_values[0]	auto[0]	auto[0]	auto[1]	88	1			T37	5		T126	1		T206	1
all_values[0]	auto[0]	auto[1]	auto[0]	128	1			T33	2		T35	4		T37	5
all_values[0]	auto[0]	auto[1]	auto[1]	80	1			T33	4		T36	3		T37	2
all_values[0]	auto[1]	auto[0]	auto[1]	166	1			T33	4		T36	1		T37	4
all_values[0]	auto[1]	auto[1]	auto[1]	159	1			T33	2		T35	1		T36	1
all_values[1]	auto[0]	auto[0]	auto[0]	143	1			T33	3		T36	1		T37	5
all_values[1]	auto[0]	auto[0]	auto[1]	79	1			T33	2		T36	1		T37	3
all_values[1]	auto[0]	auto[1]	auto[0]	139	1			T33	5		T35	2		T37	5
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T33	1		T36	2		T37	1
all_values[1]	auto[1]	auto[0]	auto[1]	180	1			T33	5		T35	3		T36	1
all_values[1]	auto[1]	auto[1]	auto[1]	152	1			T33	1		T35	2		T36	2
all_values[2]	auto[0]	auto[0]	auto[0]	153	1			T33	3		T35	1		T36	1
all_values[2]	auto[0]	auto[0]	auto[1]	76	1			T37	2		T126	1		T206	2
all_values[2]	auto[0]	auto[1]	auto[0]	153	1			T33	5		T35	1		T37	5
all_values[2]	auto[0]	auto[1]	auto[1]	77	1			T33	1		T36	1		T37	3
all_values[2]	auto[1]	auto[0]	auto[1]	178	1			T33	2		T36	2		T37	10
all_values[2]	auto[1]	auto[1]	auto[1]	141	1			T33	6		T35	5		T36	3
all_values[3]	auto[0]	auto[0]	auto[0]	134	1			T33	4		T35	5		T36	2
all_values[3]	auto[0]	auto[0]	auto[1]	87	1			T33	5		T37	3		T126	1
all_values[3]	auto[0]	auto[1]	auto[0]	130	1			T37	3		T206	2		T191	1
all_values[3]	auto[0]	auto[1]	auto[1]	75	1			T33	2		T35	1		T36	1
all_values[3]	auto[1]	auto[0]	auto[1]	188	1			T33	4		T35	1		T36	1
all_values[3]	auto[1]	auto[1]	auto[1]	164	1			T33	2		T36	3		T37	7
all_values[4]	auto[0]	auto[0]	auto[0]	170	1			T33	7		T35	3		T36	4
all_values[4]	auto[0]	auto[0]	auto[1]	54	1			T206	2		T191	1		T207	1
all_values[4]	auto[0]	auto[1]	auto[0]	150	1			T35	1		T36	2		T37	10
all_values[4]	auto[0]	auto[1]	auto[1]	77	1			T33	1		T37	3		T126	1
all_values[4]	auto[1]	auto[0]	auto[1]	160	1			T33	6		T35	2		T36	1
all_values[4]	auto[1]	auto[1]	auto[1]	167	1			T33	3		T35	1		T37	7
all_values[5]	auto[0]	auto[0]	auto[0]	242	1			T33	6		T36	4		T37	7
all_values[5]	auto[0]	auto[1]	auto[0]	196	1			T33	6		T35	2		T37	10
all_values[5]	auto[1]	auto[0]	auto[1]	176	1			T33	4		T35	1		T36	1
all_values[5]	auto[1]	auto[1]	auto[1]	164	1			T33	1		T35	4		T36	2
all_values[6]	auto[0]	auto[0]	auto[0]	145	1			T33	4		T35	2		T36	1
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T33	4		T36	2		T37	1
all_values[6]	auto[0]	auto[1]	auto[0]	117	1			T33	1		T35	1		T37	4
all_values[6]	auto[0]	auto[1]	auto[1]	83	1			T37	3		T126	1		T192	1
all_values[6]	auto[1]	auto[0]	auto[1]	204	1			T33	5		T35	4		T36	4
all_values[6]	auto[1]	auto[1]	auto[1]	156	1			T33	3		T37	6		T126	2
all_values[7]	auto[0]	auto[0]	auto[0]	170	1			T33	7		T35	4		T36	3
all_values[7]	auto[0]	auto[0]	auto[1]	87	1			T33	2		T37	2		T206	1
all_values[7]	auto[0]	auto[1]	auto[0]	153	1			T33	4		T35	1		T37	10
all_values[7]	auto[0]	auto[1]	auto[1]	53	1			T36	3		T37	2		T206	2
all_values[7]	auto[1]	auto[0]	auto[1]	161	1			T33	2		T37	3		T126	1
all_values[7]	auto[1]	auto[1]	auto[1]	154	1			T33	2		T35	2		T36	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal