Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1779

1

T5

4

T11

9

T18

1

auto[1]

1754

1

T11

3

T19

5

T28

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1927

1

T18

1

T27

1

T29

3

auto[1]

1606

1

T5

4

T11

12

T19

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2839

1

T5

4

T11

12

T19

10

auto[1]

694

1

T18

1

T27

1

T29

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	747	1			T11	1		T19	3		T27	1
valid[1]	771	1			T11	2		T19	2		T28	2
valid[2]	663	1			T5	1		T11	1		T19	2
valid[3]	684	1			T11	4		T18	1		T28	1
valid[4]	668	1			T5	3		T11	4		T19	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	142	1			T46	1		T47	1		T121	1
auto[0]	auto[0]	valid[0]	auto[1]	173	1			T19	3		T30	2		T124	1
auto[0]	auto[0]	valid[1]	auto[0]	137	1			T46	2		T47	2		T414	2
auto[0]	auto[0]	valid[1]	auto[1]	166	1			T11	2		T19	1		T28	1
auto[0]	auto[0]	valid[2]	auto[0]	120	1			T46	3		T47	4		T120	1
auto[0]	auto[0]	valid[2]	auto[1]	143	1			T5	1		T11	1		T30	1
auto[0]	auto[0]	valid[3]	auto[0]	111	1			T46	2		T47	1		T416	1
auto[0]	auto[0]	valid[3]	auto[1]	169	1			T11	4		T28	1		T30	4
auto[0]	auto[0]	valid[4]	auto[0]	121	1			T46	1		T47	1		T88	2
auto[0]	auto[0]	valid[4]	auto[1]	155	1			T5	3		T11	2		T19	1
auto[0]	auto[1]	valid[0]	auto[0]	118	1			T414	2		T121	2		T106	1
auto[0]	auto[1]	valid[0]	auto[1]	168	1			T11	1		T30	3		T124	1
auto[0]	auto[1]	valid[1]	auto[0]	137	1			T46	3		T88	1		T121	1
auto[0]	auto[1]	valid[1]	auto[1]	187	1			T19	1		T28	1		T30	2
auto[0]	auto[1]	valid[2]	auto[0]	110	1			T46	1		T47	1		T38	1
auto[0]	auto[1]	valid[2]	auto[1]	158	1			T19	2		T30	5		T122	4
auto[0]	auto[1]	valid[3]	auto[0]	121	1			T46	1		T47	2		T414	1
auto[0]	auto[1]	valid[3]	auto[1]	131	1			T30	4		T122	1		T123	4
auto[0]	auto[1]	valid[4]	auto[0]	116	1			T46	1		T88	1		T121	1
auto[0]	auto[1]	valid[4]	auto[1]	156	1			T11	2		T19	2		T30	5
auto[1]	auto[0]	valid[0]	auto[0]	78	1			T27	1		T29	1		T121	3
auto[1]	auto[0]	valid[1]	auto[0]	64	1			T29	1		T50	1		T46	1
auto[1]	auto[0]	valid[2]	auto[0]	60	1			T47	1		T120	1		T419	1
auto[1]	auto[0]	valid[3]	auto[0]	80	1			T18	1		T121	1		T411	1
auto[1]	auto[0]	valid[4]	auto[0]	60	1			T414	1		T121	1		T53	1
auto[1]	auto[1]	valid[0]	auto[0]	68	1			T414	1		T402	1		T411	1
auto[1]	auto[1]	valid[1]	auto[0]	80	1			T29	1		T47	1		T121	1
auto[1]	auto[1]	valid[2]	auto[0]	72	1			T88	1		T38	2		T405	2
auto[1]	auto[1]	valid[3]	auto[0]	72	1			T46	1		T414	1		T121	1
auto[1]	auto[1]	valid[4]	auto[0]	60	1			T88	2		T120	1		T205	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal