Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48277

1

T10

4

T18

5

T27

10

auto[1]

16113

1

T5

4

T7

48

T11

12

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47092

1

T5

4

T7

48

T10

2

auto[1]

17298

1

T10

2

T18

3

T27

5

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32959	1			T5	4		T7	30		T10	3
others[1]	5486	1			T7	5		T18	2		T27	1
others[2]	5485	1			T7	6		T10	1		T18	1
others[3]	6070	1			T7	2		T27	1		T29	10
interest[1]	3617	1			T27	1		T29	2		T30	15
interest[4]	21516	1			T5	4		T7	22		T10	3
interest[64]	10773	1			T7	5		T18	1		T27	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15735	1			T10	2		T27	2		T29	10
auto[0]	auto[0]	others[1]	2657	1			T18	1		T27	1		T29	3
auto[0]	auto[0]	others[2]	2691	1			T29	1		T86	2		T46	19
auto[0]	auto[0]	others[3]	2973	1			T29	5		T86	1		T46	20
auto[0]	auto[0]	interest[1]	1711	1			T27	1		T46	13		T47	8
auto[0]	auto[0]	interest[4]	10243	1			T10	2		T27	1		T29	4
auto[0]	auto[0]	interest[64]	5212	1			T18	1		T27	1		T29	7
auto[0]	auto[1]	others[0]	8431	1			T5	4		T7	30		T11	12
auto[0]	auto[1]	others[1]	1338	1			T7	5		T29	1		T30	28
auto[0]	auto[1]	others[2]	1354	1			T7	6		T30	27		T122	36
auto[0]	auto[1]	others[3]	1508	1			T7	2		T29	3		T30	38
auto[0]	auto[1]	interest[1]	890	1			T30	15		T122	21		T123	12
auto[0]	auto[1]	interest[4]	5607	1			T5	4		T7	22		T11	12
auto[0]	auto[1]	interest[64]	2592	1			T7	5		T29	3		T30	43
auto[1]	auto[0]	others[0]	8793	1			T10	1		T18	1		T27	3
auto[1]	auto[0]	others[1]	1491	1			T18	1		T29	2		T86	1
auto[1]	auto[0]	others[2]	1440	1			T10	1		T18	1		T27	1
auto[1]	auto[0]	others[3]	1589	1			T27	1		T29	2		T50	2
auto[1]	auto[0]	interest[1]	1016	1			T29	2		T46	5		T47	9
auto[1]	auto[0]	interest[4]	5666	1			T10	1		T18	1		T27	3
auto[1]	auto[0]	interest[64]	2969	1			T29	3		T50	1		T86	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal