Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2550119	1			T1	1		T2	1		T3	1
all_values[1]	2550119	1			T1	1		T2	1		T3	1
all_values[2]	2550119	1			T1	1		T2	1		T3	1
all_values[3]	2550119	1			T1	1		T2	1		T3	1
all_values[4]	2550119	1			T1	1		T2	1		T3	1
all_values[5]	2550119	1			T1	1		T2	1		T3	1
all_values[6]	2550119	1			T1	1		T2	1		T3	1
all_values[7]	2550119	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19962830

1

T1

8

T2

8

T3

8

auto[1]

438122

1

T25

90

T35

3105

T37

9111

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20371624

1

T1

8

T2

8

T3

8

auto[1]

29328

1

T25

67

T35

12

T58

22

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2530825	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	13859	1			T25	4		T35	4		T58	22
all_values[0]	auto[1]	auto[0]	5185	1			T25	4		T35	1		T37	1795
all_values[0]	auto[1]	auto[1]	250	1			T25	5		T37	23		T38	4
all_values[1]	auto[0]	auto[0]	2491700	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	9273	1			T25	8		T35	3		T89	131
all_values[1]	auto[1]	auto[0]	48784	1			T25	3		T35	1		T37	1796
all_values[1]	auto[1]	auto[1]	362	1			T25	4		T37	25		T38	3
all_values[2]	auto[0]	auto[0]	2435676	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	3359	1			T25	6		T89	14		T37	3
all_values[2]	auto[1]	auto[0]	110746	1			T25	12		T35	1033		T37	1796
all_values[2]	auto[1]	auto[1]	338	1			T25	1		T37	23		T38	6
all_values[3]	auto[0]	auto[0]	2498262	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	173	1			T25	4		T38	4		T192	1
all_values[3]	auto[1]	auto[0]	51493	1			T25	9		T35	1		T37	1821
all_values[3]	auto[1]	auto[1]	191	1			T25	5		T37	1		T38	4
all_values[4]	auto[0]	auto[0]	2490089	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	173	1			T25	1		T37	1		T38	4
all_values[4]	auto[1]	auto[0]	59644	1			T25	12		T35	1034		T37	1815
all_values[4]	auto[1]	auto[1]	213	1			T25	5		T37	4		T38	6
all_values[5]	auto[0]	auto[0]	2508744	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	199	1			T25	5		T35	1		T37	4
all_values[5]	auto[1]	auto[0]	41006	1			T25	7		T35	1		T37	1
all_values[5]	auto[1]	auto[1]	170	1			T25	4		T35	1		T37	3
all_values[6]	auto[0]	auto[0]	2494824	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	187	1			T25	4		T37	4		T38	2
all_values[6]	auto[1]	auto[0]	54917	1			T25	2		T37	1		T38	8
all_values[6]	auto[1]	auto[1]	191	1			T25	3		T37	2		T38	4
all_values[7]	auto[0]	auto[0]	2485297	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	190	1			T25	3		T35	1		T37	3
all_values[7]	auto[1]	auto[0]	64432	1			T25	9		T35	1031		T37	2
all_values[7]	auto[1]	auto[1]	200	1			T25	5		T35	2		T37	3