Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total tests in report: 1150
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
44.88 44.88 68.12 68.12 46.05 46.05 66.04 66.04 6.67 6.67 56.29 56.29 66.43 66.43 4.55 4.55 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.976765091
71.69 26.81 89.46 21.33 83.30 37.24 82.19 16.14 57.78 51.11 91.98 35.69 80.29 13.86 16.83 12.28 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.2845914788
80.31 8.62 91.40 1.94 88.67 5.37 84.06 1.87 86.67 28.89 94.71 2.72 83.14 2.86 33.51 16.68 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.2522326960
83.18 2.87 91.50 0.10 90.42 1.75 84.45 0.39 91.11 4.44 94.82 0.12 83.14 0.00 46.78 13.27 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.2019975584
85.32 2.14 91.58 0.07 90.65 0.24 85.24 0.79 91.11 0.00 94.96 0.14 83.29 0.14 60.40 13.61 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.2535857690
87.25 1.93 97.83 6.26 91.41 0.76 87.40 2.17 91.11 0.00 96.45 1.49 83.86 0.57 62.67 2.28 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.2487321330
88.83 1.59 97.83 0.00 91.59 0.17 87.80 0.39 91.11 0.00 96.48 0.03 92.57 8.71 64.46 1.78 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2829851985
89.76 0.92 98.16 0.33 92.64 1.06 90.55 2.76 91.11 0.00 96.94 0.46 94.14 1.57 64.75 0.30 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.4263924064
90.62 0.86 98.16 0.00 92.66 0.01 90.55 0.00 93.33 2.22 96.96 0.02 94.14 0.00 68.51 3.76 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1849613037
91.39 0.77 98.16 0.00 92.66 0.00 90.55 0.00 93.33 0.00 96.96 0.00 94.14 0.00 73.91 5.40 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.3135822159
92.08 0.70 98.30 0.14 92.66 0.00 95.28 4.72 93.33 0.00 96.97 0.02 94.14 0.00 73.91 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.1369276139
92.72 0.64 98.30 0.00 92.66 0.00 95.28 0.00 93.33 0.00 96.97 0.00 94.14 0.00 78.37 4.46 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.874891972
93.18 0.46 98.31 0.01 92.69 0.04 98.03 2.76 93.33 0.00 96.99 0.02 94.29 0.14 78.61 0.25 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.2667514461
93.58 0.40 98.31 0.00 92.69 0.00 98.03 0.00 93.33 0.00 96.99 0.00 94.29 0.00 81.39 2.77 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.276325281
93.87 0.30 98.31 0.00 92.73 0.04 98.03 0.00 93.33 0.00 96.99 0.00 94.29 0.00 83.42 2.03 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.3133814274
94.16 0.29 98.31 0.00 92.76 0.02 98.03 0.00 93.33 0.00 96.99 0.00 94.29 0.00 85.45 2.03 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.1357620099
94.42 0.25 98.31 0.00 92.76 0.00 98.03 0.00 93.33 0.00 96.99 0.00 94.29 0.00 87.23 1.78 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.3885812370
94.60 0.18 98.31 0.00 92.76 0.00 98.03 0.00 93.33 0.00 96.99 0.00 94.29 0.00 88.47 1.24 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.2459193768
94.75 0.15 98.32 0.01 92.84 0.09 98.03 0.00 93.33 0.00 97.01 0.02 94.29 0.00 89.41 0.94 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.977584105
94.89 0.14 98.32 0.00 92.84 0.00 98.03 0.00 93.33 0.00 97.01 0.00 95.29 1.00 89.41 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3666524725
95.03 0.14 98.32 0.00 92.84 0.00 98.03 0.00 93.33 0.00 97.01 0.00 95.29 0.00 90.40 0.99 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.704888857
95.15 0.12 98.35 0.03 92.88 0.04 98.03 0.00 93.33 0.00 97.07 0.07 95.29 0.00 91.09 0.69 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.2484773851
95.27 0.12 98.35 0.00 93.60 0.72 98.03 0.00 93.33 0.00 97.07 0.00 95.29 0.00 91.19 0.10 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.912907353
95.37 0.11 98.35 0.00 93.61 0.01 98.03 0.00 93.33 0.00 97.07 0.00 95.29 0.00 91.93 0.74 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.795477000
95.48 0.10 98.40 0.06 93.76 0.15 98.43 0.39 93.33 0.00 97.21 0.14 95.29 0.00 91.93 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.1487871622
95.58 0.10 98.40 0.00 93.76 0.00 98.43 0.00 93.33 0.00 97.21 0.00 95.29 0.00 92.62 0.69 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.3702272571
95.67 0.09 98.40 0.00 93.76 0.00 98.43 0.00 93.33 0.00 97.21 0.00 95.29 0.00 93.27 0.64 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.4159928331
95.75 0.08 98.40 0.00 93.79 0.02 98.43 0.00 93.33 0.00 97.21 0.00 95.29 0.00 93.81 0.54 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2806733291
95.83 0.08 98.40 0.00 93.79 0.00 98.43 0.00 93.33 0.00 97.21 0.00 95.29 0.00 94.36 0.54 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.640523471
95.91 0.08 98.40 0.00 93.79 0.00 98.43 0.00 93.33 0.00 97.21 0.00 95.43 0.14 94.75 0.40 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.239905550
95.97 0.06 98.40 0.00 93.79 0.00 98.43 0.00 93.33 0.00 97.21 0.00 95.43 0.00 95.20 0.45 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.386997870
96.03 0.06 98.40 0.00 93.79 0.00 98.43 0.00 93.33 0.00 97.21 0.00 95.43 0.00 95.64 0.45 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.797495358
96.09 0.06 98.40 0.00 93.79 0.00 98.43 0.00 93.33 0.00 97.21 0.00 95.43 0.00 96.04 0.40 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.2700515618
96.14 0.05 98.40 0.00 93.79 0.00 98.43 0.00 93.33 0.00 97.21 0.00 95.43 0.00 96.39 0.35 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.375777156
96.19 0.05 98.40 0.00 93.79 0.00 98.43 0.00 93.33 0.00 97.21 0.00 95.43 0.00 96.73 0.35 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.3781831608
96.23 0.04 98.43 0.03 93.86 0.07 98.62 0.20 93.33 0.00 97.21 0.00 95.43 0.00 96.73 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.1278810751
96.27 0.04 98.43 0.00 93.86 0.00 98.62 0.00 93.33 0.00 97.21 0.00 95.43 0.00 97.03 0.30 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.466658184
96.31 0.04 98.43 0.00 93.90 0.04 98.62 0.00 93.33 0.00 97.23 0.02 95.43 0.00 97.23 0.20 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.95308756
96.34 0.04 98.43 0.00 93.90 0.00 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 97.48 0.25 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.2963538832
96.38 0.04 98.43 0.00 93.90 0.00 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 97.72 0.25 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.1130915927
96.41 0.03 98.43 0.00 93.90 0.00 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 97.92 0.20 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.3215631936
96.44 0.03 98.43 0.00 93.90 0.00 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 98.12 0.20 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.2949125227
96.46 0.02 98.43 0.00 93.90 0.00 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 98.27 0.15 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.452455405
96.48 0.02 98.43 0.00 93.90 0.00 98.62 0.00 93.33 0.00 97.23 0.00 95.43 0.00 98.42 0.15 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.663426650
96.50 0.02 98.43 0.00 93.92 0.02 98.62 0.00 93.33 0.00 97.24 0.02 95.43 0.00 98.51 0.10 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.2793241370
96.52 0.02 98.43 0.00 93.99 0.06 98.62 0.00 93.33 0.00 97.24 0.00 95.43 0.00 98.56 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1741755493
96.53 0.01 98.43 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.43 0.00 98.66 0.10 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.3454889064
96.54 0.01 98.43 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.43 0.00 98.76 0.10 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.2896539756
96.56 0.01 98.43 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.43 0.00 98.86 0.10 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.2890348251
96.57 0.01 98.43 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.43 0.00 98.96 0.10 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.672013089
96.58 0.01 98.43 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.43 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.1187276947
96.59 0.01 98.43 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.43 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.1505338095
96.59 0.01 98.43 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.43 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.3106566183
96.60 0.01 98.43 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.43 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.3157599532
96.61 0.01 98.43 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.43 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.2905180398
96.61 0.01 98.43 0.00 93.99 0.00 98.62 0.00 93.33 0.00 97.24 0.00 95.43 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2865220256
96.62 0.01 98.43 0.00 94.01 0.02 98.62 0.00 93.33 0.00 97.26 0.02 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.3908885426
96.63 0.01 98.43 0.00 94.05 0.04 98.62 0.00 93.33 0.00 97.26 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.2299782510
96.63 0.01 98.44 0.01 94.05 0.00 98.62 0.00 93.33 0.00 97.28 0.02 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.2528703908
96.63 0.01 98.44 0.00 94.07 0.02 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1853647099
96.63 0.01 98.44 0.00 94.08 0.01 98.62 0.00 93.33 0.00 97.28 0.00 95.43 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.2677779763

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.3918507867
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.807399611
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.222200666
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.626117268
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2800605651
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1880867671
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3484894195
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.280217111
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.434731873
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.2707667424
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.1595678735
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3894070422
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2847859099
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3259545338
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.223709893
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.90108948
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.600794191
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.762527915
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.159568393
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.3076523763
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.840039123
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.907505967
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.2917149985
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.1171182521
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1825218275
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/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.1693719276
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/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.923782715
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.98196899
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2604654886
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.1891563788
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.1870113388
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.784391325
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.3848487527
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.2464713121
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.1472764498
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.2621846779
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1788060634
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.3464502172
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.3980503487
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.2609530263
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.3072168611
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.1623654809
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3771525351
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3858291850
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.1947024724
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.1254679948
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.4011024766
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3105264708
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.3188049519
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.556335089
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.3017968267
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.3857946563
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.1079177031
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.4056997015
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2540091791
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.608083122
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.1806836843
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.1656805822
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.494395841
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.3268260957
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.360678182
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1804092074
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.3893226873
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.3439216146
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.3928652748
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.1385134659
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3245962977
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.1744513574
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.2211757565
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1044488558
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.1197297643
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.488243670
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.3575652373
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2836264474
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.3222310296
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.2556454330
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.3598944390
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.4085701651
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.2594071650
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.896014592
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.1144778823
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.3088549264
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.2943602047
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.765482867
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.823471721
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.246778290
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.827440062



Total test records in report: 1150
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.1369276139 Sep 11 05:06:10 PM UTC 24 Sep 11 05:06:12 PM UTC 24 31397492 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.3583025426 Sep 11 05:06:10 PM UTC 24 Sep 11 05:06:12 PM UTC 24 35281655 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.975473235 Sep 11 05:06:10 PM UTC 24 Sep 11 05:06:12 PM UTC 24 17494305 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.1921190914 Sep 11 05:06:10 PM UTC 24 Sep 11 05:06:12 PM UTC 24 18595040 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.1487871622 Sep 11 05:06:10 PM UTC 24 Sep 11 05:06:12 PM UTC 24 26451410 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.1278810751 Sep 11 05:06:11 PM UTC 24 Sep 11 05:06:13 PM UTC 24 29593043 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.2667514461 Sep 11 05:06:11 PM UTC 24 Sep 11 05:06:13 PM UTC 24 224373343 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.1170484079 Sep 11 05:06:11 PM UTC 24 Sep 11 05:06:14 PM UTC 24 29792252 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.976765091 Sep 11 05:06:12 PM UTC 24 Sep 11 05:06:14 PM UTC 24 18112271 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.2432201914 Sep 11 05:06:12 PM UTC 24 Sep 11 05:06:14 PM UTC 24 27686148 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.1999368945 Sep 11 05:06:13 PM UTC 24 Sep 11 05:06:16 PM UTC 24 69373737 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.2487321330 Sep 11 05:06:11 PM UTC 24 Sep 11 05:06:16 PM UTC 24 141269335 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.1132105769 Sep 11 05:06:10 PM UTC 24 Sep 11 05:06:17 PM UTC 24 1523113520 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.576200932 Sep 11 05:06:12 PM UTC 24 Sep 11 05:06:17 PM UTC 24 1429023196 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3799146819 Sep 11 05:06:11 PM UTC 24 Sep 11 05:06:18 PM UTC 24 328196958 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.2845914788 Sep 11 05:06:11 PM UTC 24 Sep 11 05:06:18 PM UTC 24 855395293 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.1675126315 Sep 11 05:06:14 PM UTC 24 Sep 11 05:06:18 PM UTC 24 282883095 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.595042813 Sep 11 05:06:14 PM UTC 24 Sep 11 05:06:18 PM UTC 24 99349059 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.4151264721 Sep 11 05:06:14 PM UTC 24 Sep 11 05:06:19 PM UTC 24 1150059091 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.323308165 Sep 11 05:06:18 PM UTC 24 Sep 11 05:06:20 PM UTC 24 14168907 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.178868003 Sep 11 05:06:18 PM UTC 24 Sep 11 05:06:20 PM UTC 24 65091011 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.3483163707 Sep 11 05:06:18 PM UTC 24 Sep 11 05:06:21 PM UTC 24 153241336 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.674264621 Sep 11 05:06:15 PM UTC 24 Sep 11 05:06:21 PM UTC 24 796888789 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.3896455181 Sep 11 05:06:14 PM UTC 24 Sep 11 05:06:21 PM UTC 24 391288098 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.95308756 Sep 11 05:06:14 PM UTC 24 Sep 11 05:06:21 PM UTC 24 298164137 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.3026617757 Sep 11 05:06:11 PM UTC 24 Sep 11 05:06:22 PM UTC 24 1829397359 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.4108191949 Sep 11 05:06:20 PM UTC 24 Sep 11 05:06:23 PM UTC 24 164139733 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.3691824394 Sep 11 05:06:20 PM UTC 24 Sep 11 05:06:23 PM UTC 24 109675636 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.3406864779 Sep 11 05:06:15 PM UTC 24 Sep 11 05:06:24 PM UTC 24 158335288 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.4263924064 Sep 11 05:06:20 PM UTC 24 Sep 11 05:06:24 PM UTC 24 140562566 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.2975377561 Sep 11 05:06:11 PM UTC 24 Sep 11 05:06:25 PM UTC 24 3297220909 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.497428868 Sep 11 05:06:20 PM UTC 24 Sep 11 05:06:28 PM UTC 24 854465092 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3304514558 Sep 11 05:06:10 PM UTC 24 Sep 11 05:06:28 PM UTC 24 3785267240 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.109373698 Sep 11 05:06:26 PM UTC 24 Sep 11 05:06:29 PM UTC 24 122839286 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.2886928297 Sep 11 05:06:22 PM UTC 24 Sep 11 05:06:31 PM UTC 24 798267232 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.479051847 Sep 11 05:06:29 PM UTC 24 Sep 11 05:06:31 PM UTC 24 41986611 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.269098485 Sep 11 05:06:29 PM UTC 24 Sep 11 05:06:32 PM UTC 24 18409840 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.3907380497 Sep 11 05:06:29 PM UTC 24 Sep 11 05:06:32 PM UTC 24 146212158 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.688162559 Sep 11 05:06:24 PM UTC 24 Sep 11 05:06:32 PM UTC 24 1589221069 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.3255750364 Sep 11 05:06:22 PM UTC 24 Sep 11 05:06:32 PM UTC 24 1319579333 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.2564410878 Sep 11 05:06:20 PM UTC 24 Sep 11 05:06:33 PM UTC 24 8583989594 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.4253395686 Sep 11 05:06:31 PM UTC 24 Sep 11 05:06:34 PM UTC 24 91277560 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.2906047648 Sep 11 05:06:24 PM UTC 24 Sep 11 05:06:35 PM UTC 24 747818501 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.932144234 Sep 11 05:06:32 PM UTC 24 Sep 11 05:06:35 PM UTC 24 12447145 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.243536020 Sep 11 05:06:33 PM UTC 24 Sep 11 05:06:35 PM UTC 24 289264080 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.3687307142 Sep 11 05:06:24 PM UTC 24 Sep 11 05:06:36 PM UTC 24 1037719411 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.3446201710 Sep 11 05:06:34 PM UTC 24 Sep 11 05:06:37 PM UTC 24 106231681 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1445636605 Sep 11 05:06:36 PM UTC 24 Sep 11 05:06:41 PM UTC 24 93610657 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.3932732625 Sep 11 05:06:24 PM UTC 24 Sep 11 05:06:41 PM UTC 24 50324872784 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.1755412160 Sep 11 05:06:37 PM UTC 24 Sep 11 05:06:42 PM UTC 24 81706289 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.1505338095 Sep 11 05:06:10 PM UTC 24 Sep 11 05:06:43 PM UTC 24 10213858370 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.2528703908 Sep 11 05:06:10 PM UTC 24 Sep 11 05:06:44 PM UTC 24 13860578766 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.1970711318 Sep 11 05:06:24 PM UTC 24 Sep 11 05:06:46 PM UTC 24 1309478893 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.2181289781 Sep 11 05:06:24 PM UTC 24 Sep 11 05:06:48 PM UTC 24 10974667666 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3722853839 Sep 11 05:06:34 PM UTC 24 Sep 11 05:06:50 PM UTC 24 7167796068 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.2013844694 Sep 11 05:06:47 PM UTC 24 Sep 11 05:06:50 PM UTC 24 310856294 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.340850216 Sep 11 05:06:49 PM UTC 24 Sep 11 05:06:51 PM UTC 24 33021248 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.971721775 Sep 11 05:06:36 PM UTC 24 Sep 11 05:06:52 PM UTC 24 525242212 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.1256549880 Sep 11 05:06:51 PM UTC 24 Sep 11 05:06:53 PM UTC 24 18140651 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.1905136199 Sep 11 05:06:51 PM UTC 24 Sep 11 05:06:54 PM UTC 24 35304152 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.3398481892 Sep 11 05:06:35 PM UTC 24 Sep 11 05:06:54 PM UTC 24 4361752919 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.1628211616 Sep 11 05:06:24 PM UTC 24 Sep 11 05:06:55 PM UTC 24 52722955444 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.478670141 Sep 11 05:06:41 PM UTC 24 Sep 11 05:06:56 PM UTC 24 1688633091 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.2522326960 Sep 11 05:06:11 PM UTC 24 Sep 11 05:06:56 PM UTC 24 2291249426 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.1222047443 Sep 11 05:06:54 PM UTC 24 Sep 11 05:06:57 PM UTC 24 209901866 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.3142964023 Sep 11 05:06:54 PM UTC 24 Sep 11 05:06:57 PM UTC 24 48649422 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2214014597 Sep 11 05:06:52 PM UTC 24 Sep 11 05:06:58 PM UTC 24 776064220 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.755427288 Sep 11 05:06:35 PM UTC 24 Sep 11 05:06:59 PM UTC 24 2415376260 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.969611410 Sep 11 05:06:10 PM UTC 24 Sep 11 05:07:00 PM UTC 24 194776223247 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.589770667 Sep 11 05:06:33 PM UTC 24 Sep 11 05:07:02 PM UTC 24 1413618304 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.1401283328 Sep 11 05:06:58 PM UTC 24 Sep 11 05:07:06 PM UTC 24 1300244768 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.3361747143 Sep 11 05:06:12 PM UTC 24 Sep 11 05:07:06 PM UTC 24 13162821570 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.2097453046 Sep 11 05:06:56 PM UTC 24 Sep 11 05:07:09 PM UTC 24 1236087697 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.1187276947 Sep 11 05:06:11 PM UTC 24 Sep 11 05:07:11 PM UTC 24 4684340684 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.1495283878 Sep 11 05:06:10 PM UTC 24 Sep 11 05:07:12 PM UTC 24 12700813036 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.2894000807 Sep 11 05:07:01 PM UTC 24 Sep 11 05:07:13 PM UTC 24 353531184 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.971064754 Sep 11 05:07:11 PM UTC 24 Sep 11 05:07:14 PM UTC 24 315068278 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.1754001323 Sep 11 05:06:36 PM UTC 24 Sep 11 05:07:14 PM UTC 24 5244106108 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.3947503889 Sep 11 05:07:13 PM UTC 24 Sep 11 05:07:15 PM UTC 24 21489565 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.277414388 Sep 11 05:07:13 PM UTC 24 Sep 11 05:07:16 PM UTC 24 17101032 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.4050645245 Sep 11 05:06:16 PM UTC 24 Sep 11 05:07:16 PM UTC 24 9923846174 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.2472758647 Sep 11 05:06:53 PM UTC 24 Sep 11 05:07:16 PM UTC 24 13167111249 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.4021344026 Sep 11 05:07:15 PM UTC 24 Sep 11 05:07:17 PM UTC 24 44637287 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.3948661472 Sep 11 05:06:55 PM UTC 24 Sep 11 05:07:17 PM UTC 24 12738109282 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.3863781947 Sep 11 05:06:58 PM UTC 24 Sep 11 05:07:18 PM UTC 24 2788377357 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.3754658318 Sep 11 05:07:17 PM UTC 24 Sep 11 05:07:19 PM UTC 24 22223062 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.3873628493 Sep 11 05:06:38 PM UTC 24 Sep 11 05:07:20 PM UTC 24 2208267468 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.3450129435 Sep 11 05:07:17 PM UTC 24 Sep 11 05:07:20 PM UTC 24 347737824 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.1734328735 Sep 11 05:06:58 PM UTC 24 Sep 11 05:07:21 PM UTC 24 1417678934 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.2019975584 Sep 11 05:06:11 PM UTC 24 Sep 11 05:07:21 PM UTC 24 2554523620 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.121685260 Sep 11 05:06:55 PM UTC 24 Sep 11 05:07:22 PM UTC 24 28473353071 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.1332407405 Sep 11 05:07:20 PM UTC 24 Sep 11 05:07:25 PM UTC 24 423719409 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.430302755 Sep 11 05:07:18 PM UTC 24 Sep 11 05:07:25 PM UTC 24 589651677 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2806733291 Sep 11 05:06:25 PM UTC 24 Sep 11 05:07:25 PM UTC 24 3053132126 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.4117438489 Sep 11 05:07:25 PM UTC 24 Sep 11 05:07:28 PM UTC 24 14723911 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.3591975512 Sep 11 05:07:26 PM UTC 24 Sep 11 05:07:28 PM UTC 24 40932415 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.2354828406 Sep 11 05:07:17 PM UTC 24 Sep 11 05:07:30 PM UTC 24 1605563328 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.923782715 Sep 11 05:07:28 PM UTC 24 Sep 11 05:07:30 PM UTC 24 46020696 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.2753223870 Sep 11 05:07:20 PM UTC 24 Sep 11 05:07:32 PM UTC 24 2310207193 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.1974382714 Sep 11 05:07:22 PM UTC 24 Sep 11 05:07:32 PM UTC 24 1039190917 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.1626884340 Sep 11 05:07:17 PM UTC 24 Sep 11 05:07:32 PM UTC 24 5021052021 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.3848487527 Sep 11 05:07:31 PM UTC 24 Sep 11 05:07:33 PM UTC 24 28134261 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.2464713121 Sep 11 05:07:31 PM UTC 24 Sep 11 05:07:33 PM UTC 24 84192469 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.2622537944 Sep 11 05:07:00 PM UTC 24 Sep 11 05:07:35 PM UTC 24 4478118871 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3744139318 Sep 11 05:07:18 PM UTC 24 Sep 11 05:07:35 PM UTC 24 12786053341 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.375777156 Sep 11 05:07:09 PM UTC 24 Sep 11 05:07:38 PM UTC 24 6768901768 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.3278517467 Sep 11 05:07:21 PM UTC 24 Sep 11 05:07:38 PM UTC 24 1038912540 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2920577932 Sep 11 05:07:16 PM UTC 24 Sep 11 05:07:38 PM UTC 24 17157382909 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.784391325 Sep 11 05:07:29 PM UTC 24 Sep 11 05:07:38 PM UTC 24 5179576678 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.98196899 Sep 11 05:07:33 PM UTC 24 Sep 11 05:07:39 PM UTC 24 1386323044 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2604654886 Sep 11 05:07:32 PM UTC 24 Sep 11 05:07:41 PM UTC 24 1871943316 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.772849322 Sep 11 05:07:37 PM UTC 24 Sep 11 05:07:42 PM UTC 24 465079601 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.1693719276 Sep 11 05:07:33 PM UTC 24 Sep 11 05:07:44 PM UTC 24 502822324 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1270219870 Sep 11 05:07:36 PM UTC 24 Sep 11 05:07:45 PM UTC 24 4342641318 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.1055854823 Sep 11 05:07:43 PM UTC 24 Sep 11 05:07:45 PM UTC 24 22668565 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.1279524766 Sep 11 05:07:19 PM UTC 24 Sep 11 05:07:46 PM UTC 24 6428220782 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.1472764498 Sep 11 05:07:34 PM UTC 24 Sep 11 05:07:47 PM UTC 24 4244524036 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.3464502172 Sep 11 05:07:44 PM UTC 24 Sep 11 05:07:47 PM UTC 24 52512536 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.246778290 Sep 11 05:08:51 PM UTC 24 Sep 11 05:08:53 PM UTC 24 80194561 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.1623654809 Sep 11 05:07:45 PM UTC 24 Sep 11 05:07:48 PM UTC 24 229307052 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.1891563788 Sep 11 05:07:39 PM UTC 24 Sep 11 05:07:49 PM UTC 24 220271111 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.3188049519 Sep 11 05:07:48 PM UTC 24 Sep 11 05:07:50 PM UTC 24 53172261 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.3105264708 Sep 11 05:07:48 PM UTC 24 Sep 11 05:07:51 PM UTC 24 166261133 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.4231388286 Sep 11 05:07:22 PM UTC 24 Sep 11 05:07:54 PM UTC 24 2350973146 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.1870113388 Sep 11 05:07:29 PM UTC 24 Sep 11 05:07:57 PM UTC 24 6452220592 ps
T253 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.2637091269 Sep 11 05:06:14 PM UTC 24 Sep 11 05:07:59 PM UTC 24 43166233596 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.2320516832 Sep 11 05:07:23 PM UTC 24 Sep 11 05:07:59 PM UTC 24 20635145683 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.4011024766 Sep 11 05:07:47 PM UTC 24 Sep 11 05:07:59 PM UTC 24 4184560721 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3771525351 Sep 11 05:07:50 PM UTC 24 Sep 11 05:08:00 PM UTC 24 972991165 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.3072168611 Sep 11 05:07:52 PM UTC 24 Sep 11 05:08:00 PM UTC 24 345238028 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.2709804344 Sep 11 05:07:34 PM UTC 24 Sep 11 05:08:46 PM UTC 24 9878534757 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.3702272571 Sep 11 05:06:16 PM UTC 24 Sep 11 05:08:03 PM UTC 24 4447682100 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1849613037 Sep 11 05:06:11 PM UTC 24 Sep 11 05:08:03 PM UTC 24 11848248026 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.556335089 Sep 11 05:07:54 PM UTC 24 Sep 11 05:08:07 PM UTC 24 2002489262 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.2609530263 Sep 11 05:07:51 PM UTC 24 Sep 11 05:08:10 PM UTC 24 6118218550 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.2621846779 Sep 11 05:08:08 PM UTC 24 Sep 11 05:08:10 PM UTC 24 13456533 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.1947024724 Sep 11 05:08:00 PM UTC 24 Sep 11 05:08:11 PM UTC 24 687394234 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.1079177031 Sep 11 05:08:11 PM UTC 24 Sep 11 05:08:13 PM UTC 24 16228021 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.3268260957 Sep 11 05:08:11 PM UTC 24 Sep 11 05:08:14 PM UTC 24 100876332 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3245962977 Sep 11 05:08:14 PM UTC 24 Sep 11 05:08:16 PM UTC 24 103263929 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.1357620099 Sep 11 05:07:47 PM UTC 24 Sep 11 05:08:16 PM UTC 24 13498429756 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.1385134659 Sep 11 05:08:17 PM UTC 24 Sep 11 05:08:20 PM UTC 24 23371782 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.2472972213 Sep 11 05:06:59 PM UTC 24 Sep 11 05:08:23 PM UTC 24 5435572015 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3858291850 Sep 11 05:07:49 PM UTC 24 Sep 11 05:08:23 PM UTC 24 8114089987 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.3439216146 Sep 11 05:08:14 PM UTC 24 Sep 11 05:08:23 PM UTC 24 479707339 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.466658184 Sep 11 05:07:59 PM UTC 24 Sep 11 05:08:24 PM UTC 24 1515166930 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1804092074 Sep 11 05:08:17 PM UTC 24 Sep 11 05:08:24 PM UTC 24 227411714 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1788060634 Sep 11 05:07:57 PM UTC 24 Sep 11 05:08:29 PM UTC 24 34795991531 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.3928652748 Sep 11 05:08:12 PM UTC 24 Sep 11 05:08:30 PM UTC 24 3907121633 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.1744513574 Sep 11 05:08:24 PM UTC 24 Sep 11 05:08:30 PM UTC 24 1328978807 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.3857946563 Sep 11 05:08:25 PM UTC 24 Sep 11 05:08:31 PM UTC 24 694261122 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.1806836843 Sep 11 05:08:25 PM UTC 24 Sep 11 05:08:31 PM UTC 24 127491394 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.360678182 Sep 11 05:08:21 PM UTC 24 Sep 11 05:08:36 PM UTC 24 4494340200 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1880004523 Sep 11 05:07:06 PM UTC 24 Sep 11 05:08:38 PM UTC 24 13368063412 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.3017968267 Sep 11 05:08:38 PM UTC 24 Sep 11 05:08:41 PM UTC 24 44915040 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.1197297643 Sep 11 05:08:42 PM UTC 24 Sep 11 05:08:44 PM UTC 24 61883241 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.2594071650 Sep 11 05:08:45 PM UTC 24 Sep 11 05:08:47 PM UTC 24 31977689 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.3893226873 Sep 11 05:08:30 PM UTC 24 Sep 11 05:08:50 PM UTC 24 1372009498 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.3980503487 Sep 11 05:08:01 PM UTC 24 Sep 11 05:08:54 PM UTC 24 8187923269 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.1656805822 Sep 11 05:08:24 PM UTC 24 Sep 11 05:08:54 PM UTC 24 1494600494 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.823471721 Sep 11 05:08:54 PM UTC 24 Sep 11 05:08:56 PM UTC 24 59649879 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.1364020101 Sep 11 05:07:39 PM UTC 24 Sep 11 05:08:57 PM UTC 24 9298705267 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.494395841 Sep 11 05:08:24 PM UTC 24 Sep 11 05:08:58 PM UTC 24 2708447199 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.765482867 Sep 11 05:08:47 PM UTC 24 Sep 11 05:08:59 PM UTC 24 15667603986 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.4056997015 Sep 11 05:08:31 PM UTC 24 Sep 11 05:08:59 PM UTC 24 4871232913 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.874891972 Sep 11 05:06:16 PM UTC 24 Sep 11 05:09:00 PM UTC 24 38370293963 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.2943602047 Sep 11 05:08:48 PM UTC 24 Sep 11 05:09:00 PM UTC 24 3727770778 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.1338379842 Sep 11 05:07:39 PM UTC 24 Sep 11 05:09:04 PM UTC 24 4979464019 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.3598944390 Sep 11 05:08:56 PM UTC 24 Sep 11 05:09:05 PM UTC 24 2348967398 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.896014592 Sep 11 05:08:55 PM UTC 24 Sep 11 05:09:06 PM UTC 24 7412592267 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.1144778823 Sep 11 05:08:55 PM UTC 24 Sep 11 05:09:07 PM UTC 24 2435745420 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.2211757565 Sep 11 05:09:08 PM UTC 24 Sep 11 05:09:10 PM UTC 24 23150542 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.3222310296 Sep 11 05:09:00 PM UTC 24 Sep 11 05:09:12 PM UTC 24 1417361002 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.1402317827 Sep 11 05:09:11 PM UTC 24 Sep 11 05:09:14 PM UTC 24 13528942 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.167167263 Sep 11 05:09:13 PM UTC 24 Sep 11 05:09:16 PM UTC 24 34663638 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2540091791 Sep 11 05:08:31 PM UTC 24 Sep 11 05:09:16 PM UTC 24 4053917522 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.3781831608 Sep 11 05:08:30 PM UTC 24 Sep 11 05:09:16 PM UTC 24 2146858651 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.1694766242 Sep 11 05:09:13 PM UTC 24 Sep 11 05:09:17 PM UTC 24 1394294992 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.648557813 Sep 11 05:09:15 PM UTC 24 Sep 11 05:09:18 PM UTC 24 139613093 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.1160448337 Sep 11 05:09:17 PM UTC 24 Sep 11 05:09:21 PM UTC 24 181961139 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.3088549264 Sep 11 05:09:01 PM UTC 24 Sep 11 05:09:22 PM UTC 24 1281934817 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.2735876660 Sep 11 05:09:17 PM UTC 24 Sep 11 05:09:23 PM UTC 24 322172575 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.580702020 Sep 11 05:09:18 PM UTC 24 Sep 11 05:09:24 PM UTC 24 557525205 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1044488558 Sep 11 05:08:59 PM UTC 24 Sep 11 05:09:25 PM UTC 24 2130839464 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.2535857690 Sep 11 05:07:42 PM UTC 24 Sep 11 05:09:31 PM UTC 24 4082392700 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.246054264 Sep 11 05:09:18 PM UTC 24 Sep 11 05:09:31 PM UTC 24 635038913 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.988575351 Sep 11 05:09:32 PM UTC 24 Sep 11 05:09:34 PM UTC 24 41969821 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.3030337260 Sep 11 05:09:22 PM UTC 24 Sep 11 05:09:34 PM UTC 24 358420026 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.795477000 Sep 11 05:07:59 PM UTC 24 Sep 11 05:09:36 PM UTC 24 4336112912 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.3622381898 Sep 11 05:09:35 PM UTC 24 Sep 11 05:09:37 PM UTC 24 119744222 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.431381344 Sep 11 05:09:35 PM UTC 24 Sep 11 05:09:38 PM UTC 24 73035424 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.2710362712 Sep 11 05:09:17 PM UTC 24 Sep 11 05:09:40 PM UTC 24 23186580144 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.3674237979 Sep 11 05:09:24 PM UTC 24 Sep 11 05:09:40 PM UTC 24 1171613339 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.1500382518 Sep 11 05:09:38 PM UTC 24 Sep 11 05:09:41 PM UTC 24 24572212 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.1011550939 Sep 11 05:09:21 PM UTC 24 Sep 11 05:09:43 PM UTC 24 2997240343 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.2882451023 Sep 11 05:09:41 PM UTC 24 Sep 11 05:09:43 PM UTC 24 88002872 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3847884910 Sep 11 05:09:36 PM UTC 24 Sep 11 05:09:47 PM UTC 24 5143991820 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.3106566183 Sep 11 05:09:26 PM UTC 24 Sep 11 05:09:48 PM UTC 24 4132970389 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.1724223421 Sep 11 05:09:58 PM UTC 24 Sep 11 05:10:22 PM UTC 24 2662415218 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.827440062 Sep 11 05:08:57 PM UTC 24 Sep 11 05:09:50 PM UTC 24 24064888348 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.1456744066 Sep 11 05:09:44 PM UTC 24 Sep 11 05:09:52 PM UTC 24 416867518 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.3016518893 Sep 11 05:09:48 PM UTC 24 Sep 11 05:09:53 PM UTC 24 77755537 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.856548045 Sep 11 05:09:17 PM UTC 24 Sep 11 05:09:53 PM UTC 24 6644456725 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.3135822159 Sep 11 05:08:02 PM UTC 24 Sep 11 05:09:54 PM UTC 24 25990819604 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.3931511429 Sep 11 05:09:38 PM UTC 24 Sep 11 05:09:54 PM UTC 24 4940487422 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.3860073017 Sep 11 05:09:46 PM UTC 24 Sep 11 05:09:55 PM UTC 24 3609892076 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.1232857006 Sep 11 05:09:42 PM UTC 24 Sep 11 05:09:55 PM UTC 24 2518479234 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.1254679948 Sep 11 05:08:05 PM UTC 24 Sep 11 05:09:55 PM UTC 24 6900666423 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.1130915927 Sep 11 05:08:37 PM UTC 24 Sep 11 05:09:57 PM UTC 24 35456808428 ps
T252 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.3123925620 Sep 11 05:09:17 PM UTC 24 Sep 11 05:09:57 PM UTC 24 5359953752 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.2693841552 Sep 11 05:09:56 PM UTC 24 Sep 11 05:09:58 PM UTC 24 13851494 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.1988154606 Sep 11 05:09:56 PM UTC 24 Sep 11 05:09:58 PM UTC 24 27833246 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.2005767599 Sep 11 05:09:56 PM UTC 24 Sep 11 05:09:58 PM UTC 24 128560919 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.2139112660 Sep 11 05:09:58 PM UTC 24 Sep 11 05:10:00 PM UTC 24 19981811 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.2604984311 Sep 11 05:09:58 PM UTC 24 Sep 11 05:10:01 PM UTC 24 200902991 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1702944427 Sep 11 05:09:51 PM UTC 24 Sep 11 05:10:02 PM UTC 24 524383511 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1769789145 Sep 11 05:09:59 PM UTC 24 Sep 11 05:10:05 PM UTC 24 751978455 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.4165162939 Sep 11 05:09:56 PM UTC 24 Sep 11 05:10:05 PM UTC 24 3796779529 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.4085701651 Sep 11 05:08:57 PM UTC 24 Sep 11 05:10:07 PM UTC 24 29866836087 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.2556454330 Sep 11 05:09:00 PM UTC 24 Sep 11 05:10:08 PM UTC 24 19294897587 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.730446682 Sep 11 05:10:00 PM UTC 24 Sep 11 05:10:10 PM UTC 24 7775042451 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.3683340853 Sep 11 05:10:02 PM UTC 24 Sep 11 05:10:11 PM UTC 24 5687788156 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.2000156823 Sep 11 05:09:49 PM UTC 24 Sep 11 05:10:11 PM UTC 24 3050848781 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.2267667699 Sep 11 05:10:01 PM UTC 24 Sep 11 05:10:12 PM UTC 24 1239156748 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.315406490 Sep 11 05:07:23 PM UTC 24 Sep 11 05:10:12 PM UTC 24 19394054324 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3205625524 Sep 11 05:09:59 PM UTC 24 Sep 11 05:10:12 PM UTC 24 516844137 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.618721056 Sep 11 05:10:12 PM UTC 24 Sep 11 05:10:15 PM UTC 24 33369054 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.1161752074 Sep 11 05:10:13 PM UTC 24 Sep 11 05:10:15 PM UTC 24 52997150 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.1639480270 Sep 11 05:09:42 PM UTC 24 Sep 11 05:10:15 PM UTC 24 28117495063 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.683376643 Sep 11 05:10:06 PM UTC 24 Sep 11 05:10:16 PM UTC 24 132655308 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.3984554840 Sep 11 05:10:14 PM UTC 24 Sep 11 05:10:16 PM UTC 24 236957880 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.3283494604 Sep 11 05:10:16 PM UTC 24 Sep 11 05:10:18 PM UTC 24 10636732 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.1725626003 Sep 11 05:09:14 PM UTC 24 Sep 11 05:10:18 PM UTC 24 69742608538 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.1890436474 Sep 11 05:07:03 PM UTC 24 Sep 11 05:10:20 PM UTC 24 80771612291 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.560048227 Sep 11 05:10:14 PM UTC 24 Sep 11 05:10:21 PM UTC 24 486616077 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.3202014052 Sep 11 05:10:08 PM UTC 24 Sep 11 05:10:21 PM UTC 24 877909925 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.1865363504 Sep 11 05:10:12 PM UTC 24 Sep 11 05:10:23 PM UTC 24 312337146 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.2125676902 Sep 11 05:10:03 PM UTC 24 Sep 11 05:10:24 PM UTC 24 4369744818 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.2622792198 Sep 11 05:10:16 PM UTC 24 Sep 11 05:10:25 PM UTC 24 204737186 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.2580907964 Sep 11 05:10:19 PM UTC 24 Sep 11 05:10:26 PM UTC 24 641826811 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.2935857802 Sep 11 05:07:23 PM UTC 24 Sep 11 05:10:27 PM UTC 24 16170677283 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.3813527495 Sep 11 05:10:21 PM UTC 24 Sep 11 05:10:30 PM UTC 24 347862571 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.123660727 Sep 11 05:10:31 PM UTC 24 Sep 11 05:10:33 PM UTC 24 35419888 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2290229916 Sep 11 05:10:17 PM UTC 24 Sep 11 05:10:34 PM UTC 24 11430522460 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.4062883037 Sep 11 05:10:17 PM UTC 24 Sep 11 05:10:35 PM UTC 24 5242712150 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.1471855511 Sep 11 05:10:34 PM UTC 24 Sep 11 05:10:37 PM UTC 24 16116991 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.797495358 Sep 11 05:06:25 PM UTC 24 Sep 11 05:10:37 PM UTC 24 24407429931 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.4083016884 Sep 11 05:10:21 PM UTC 24 Sep 11 05:10:37 PM UTC 24 6595273646 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.2125486710 Sep 11 05:10:35 PM UTC 24 Sep 11 05:10:38 PM UTC 24 34742641 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.608083122 Sep 11 05:08:32 PM UTC 24 Sep 11 05:10:40 PM UTC 24 18880590321 ps
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