Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	37081	1			T16	4		T17	2		T21	79
auto[SpiFlashAddrCfg]	7810	1			T13	2		T16	6		T21	2
auto[SpiFlashAddr3b]	9373	1			T13	4		T16	2		T21	6
auto[SpiFlashAddr4b]	7749	1			T13	8		T16	8		T24	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35342

1

T16

10

T17

2

T21

87

auto[1]

26671

1

T13

14

T16

10

T53

10

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33073

1

T13

10

T16

11

T21

75

auto[1]

28940

1

T13

4

T16

9

T17

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41870	1			T13	2		T16	9		T17	2
values[1]	1092	1			T16	1		T61	6		T35	6
values[2]	1568	1			T53	2		T55	2		T52	1
values[3]	1462	1			T61	2		T35	2		T51	6
values[4]	1491	1			T16	1		T24	2		T57	2
values[5]	1510	1			T13	2		T16	3		T21	6
values[6]	1522	1			T35	2		T51	10		T62	2
values[7]	1547	1			T13	6		T16	1		T21	2
values[8]	9951	1			T13	4		T16	5		T23	1

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28726

1

T13

14

T16

20

T17

2

auto[1]

33287

1

T23

1

T92

1

T52

20

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58550

1

T13

12

T16

19

T17

2

write

3463

1

T13

2

T16

1

T21

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19800

1

T13

8

T16

11

T21

10

valids[0x1]

42213

1

T13

6

T16

9

T17

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1620	1			T16	1		T55	4		T52	2
internal_process_ops[0x5a]	1540	1			T16	1		T57	2		T35	8
internal_process_ops[0x05]	22573	1			T16	1		T21	73		T57	2
internal_process_ops[0x35]	1627	1			T17	2		T21	2		T22	4
internal_process_ops[0x15]	1575	1			T22	4		T55	2		T52	1
internal_process_ops[0x03]	1109	1			T16	1		T178	2		T137	4
internal_process_ops[0x0b]	1065	1			T13	2		T22	2		T24	2
internal_process_ops[0x3b]	1042	1			T13	2		T16	1		T21	6
internal_process_ops[0x6b]	1066	1			T16	1		T23	1		T92	1
internal_process_ops[0xbb]	1024	1			T16	1		T53	2		T56	2
internal_process_ops[0xeb]	1101	1			T16	2		T21	2		T24	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60260

1

T13

12

T16

19

T17

2

auto[1]

1753

1

T13

2

T16

1

T53

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59521

1

T13

14

T16

19

T17

2

auto[1]

2492

1

T16

1

T21

2

T55

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9423

1

T16

2

T17

2

T21

77

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6029

1

T16

2

T53

2

T61

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1941

1

T16

3

T21

2

T24

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1732

1

T13

2

T16

3

T53

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2407

1

T21

6

T22

2

T24

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2031

1

T13

4

T16

2

T61

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1953

1

T16

5

T24

2

T55

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1664

1

T13

6

T16

2

T53

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

121

1

T21

2

T179

2

T180

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

102

1

T65

1

T67

1

T38

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

98

1

T65

2

T66

3

T38

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

94

1

T53

2

T66

2

T67

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

125

1

T62

2

T65

1

T66

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

70

1

T181

1

T182

2

T50

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

75

1

T66

2

T38

4

T68

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

97

1

T37

1

T66

1

T67

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

107

1

T183

2

T68

1

T184

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

98

1

T58

2

T65

2

T66

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

71

1

T67

4

T38

2

T68

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

84

1

T63

2

T65

1

T66

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

111

1

T60

4

T66

1

T67

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

96

1

T37

1

T67

2

T68

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

69

1

T58

5

T65

1

T67

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

128

1

T13

2

T16

1

T53

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12532

1

T52

5

T35

124

T51

237

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8228

1

T52

3

T35

149

T51

219

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1649

1

T23

1

T92

1

T35

7

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1626

1

T52

3

T35

11

T51

25

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2032

1

T52

2

T35

13

T51

33

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2037

1

T52

2

T35

19

T51

23

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1632

1

T35

12

T51

19

T48

13

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1634

1

T35

10

T51

26

T48

15

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

92

1

T48

2

T89

1

T185

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

106

1

T35

1

T88

1

T107

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

121

1

T51

3

T186

2

T99

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

135

1

T51

1

T48

1

T187

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

117

1

T35

1

T51

2

T88

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

127

1

T52

3

T51

3

T48

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

121

1

T35

4

T51

2

T107

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

130

1

T35

3

T51

1

T187

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

113

1

T52

2

T51

1

T48

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

133

1

T51

4

T188

2

T189

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

127

1

T51

2

T48

1

T89

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

133

1

T51

3

T48

1

T88

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

140

1

T35

3

T48

2

T88

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

115

1

T35

2

T48

2

T88

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

102

1

T35

2

T48

2

T106

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

105

1

T35

1

T88

2

T189

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3631	1			T16	3		T21	2		T53	2
auto[0]	values[0]	valids[0x1]	14567	1			T13	2		T16	6		T17	2
auto[0]	values[1]	valids[0x1]	534	1			T16	1		T61	6		T58	3
auto[0]	values[2]	valids[0x0]	559	1			T53	2		T55	2		T179	2
auto[0]	values[2]	valids[0x1]	259	1			T65	3		T190	2		T66	1
auto[0]	values[3]	valids[0x0]	513	1			T58	7		T65	3		T191	2
auto[0]	values[3]	valids[0x1]	285	1			T61	2		T62	2		T58	1
auto[0]	values[4]	valids[0x0]	525	1			T16	1		T24	2		T57	2
auto[0]	values[4]	valids[0x1]	277	1			T125	6		T58	3		T65	1
auto[0]	values[5]	valids[0x0]	494	1			T13	2		T16	2		T21	6
auto[0]	values[5]	valids[0x1]	283	1			T16	1		T65	2		T66	3
auto[0]	values[6]	valids[0x0]	499	1			T58	1		T65	6		T91	6
auto[0]	values[6]	valids[0x1]	313	1			T62	2		T58	3		T90	2
auto[0]	values[7]	valids[0x0]	474	1			T13	4		T16	1		T21	2
auto[0]	values[7]	valids[0x1]	296	1			T13	2		T178	10		T58	2
auto[0]	values[8]	valids[0x0]	3285	1			T13	2		T16	4		T24	4
auto[0]	values[8]	valids[0x1]	1932	1			T13	2		T16	1		T24	2
auto[1]	values[0]	valids[0x0]	4416	1			T52	5		T35	23		T51	45
auto[1]	values[0]	valids[0x1]	19256	1			T52	8		T35	280		T51	436
auto[1]	values[1]	valids[0x1]	558	1			T35	6		T51	9		T48	3
auto[1]	values[2]	valids[0x0]	460	1			T52	1		T35	1		T51	3
auto[1]	values[2]	valids[0x1]	290	1			T35	4		T51	2		T48	1
auto[1]	values[3]	valids[0x0]	394	1			T35	1		T51	5		T48	2
auto[1]	values[3]	valids[0x1]	270	1			T35	1		T51	1		T89	3
auto[1]	values[4]	valids[0x0]	403	1			T92	1		T35	6		T51	11
auto[1]	values[4]	valids[0x1]	286	1			T35	2		T51	8		T48	7
auto[1]	values[5]	valids[0x0]	446	1			T35	1		T51	3		T88	1
auto[1]	values[5]	valids[0x1]	287	1			T35	4		T51	9		T89	2
auto[1]	values[6]	valids[0x0]	432	1			T35	2		T51	8		T48	2
auto[1]	values[6]	valids[0x1]	278	1			T51	2		T88	2		T185	1
auto[1]	values[7]	valids[0x0]	492	1			T35	3		T51	13		T88	3
auto[1]	values[7]	valids[0x1]	285	1			T35	2		T51	2		T48	1
auto[1]	values[8]	valids[0x0]	2777	1			T23	1		T52	6		T35	16
auto[1]	values[8]	valids[0x1]	1957	1			T35	10		T51	26		T48	22