Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3682513

1

T13

1

T15

1532

T16

553

auto[1]

30587

1

T16

7

T21

73

T55

60

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1229042

1

T13

1

T15

1532

T16

48

auto[1]

2484058

1

T16

512

T21

137

T22

1120

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	672413	1			T13	1		T15	736		T16	19
auto[524288:1048575]	470599	1			T22	755		T23	1		T64	11
auto[1048576:1572863]	452826	1			T16	2		T22	9		T23	9
auto[1572864:2097151]	455208	1			T16	539		T56	4		T178	1079
auto[2097152:2621439]	423919	1			T15	2		T22	14		T56	3
auto[2621440:3145727]	416041	1			T129	1818		T56	2971		T178	976
auto[3145728:3670015]	384352	1			T23	22		T64	7		T56	1296
auto[3670016:4194303]	437742	1			T15	794		T22	3		T56	12

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2518242

1

T13

1

T15

3

T16

559

auto[1]

1194858

1

T15

1529

T16

1

T21

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3270224

1

T13

1

T15

1532

T16

560

auto[1]

442876

1

T64

5

T52

173

T35

258

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	235293	1			T13	1		T15	736		T16	19
auto[0]	auto[0]	auto[0:524287]	auto[1]	367611	1			T21	66		T22	531		T55	4672
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	149672	1			T22	178		T23	1		T64	6
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	267117	1			T22	577		T35	5		T51	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	148573	1			T22	6		T23	9		T64	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	246855	1			T22	3		T35	2614		T51	838
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	165469	1			T16	22		T56	4		T178	1079
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	226740	1			T16	512		T35	5		T51	387
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	135294	1			T15	2		T22	6		T56	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	222946	1			T22	8		T35	1		T48	128
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	115741	1			T129	1818		T56	2971		T178	976
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	240776	1			T35	362		T51	2442		T48	512
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	129879	1			T23	22		T64	7		T56	1296
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	214195	1			T35	1025		T51	770		T48	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	133702	1			T15	794		T22	2		T56	12
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	244347	1			T22	1		T35	2990		T51	772
auto[0]	auto[1]	auto[0:524287]	auto[0]	620	1			T52	28		T51	2		T48	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	63372	1			T52	128		T35	256		T51	256
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1348	1			T64	5		T35	1		T88	20
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	49669	1			T187	680		T186	256		T99	513
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1513	1			T58	1		T107	1		T187	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	52333	1			T58	769		T187	4		T189	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	526	1			T35	1		T51	5		T88	11
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	57703	1			T51	2		T88	256		T65	773
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	2771	1			T52	5		T51	1		T88	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	59063	1			T89	128		T65	256		T187	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1632	1			T51	2		T88	2		T275	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	54450	1			T107	183		T188	256		T273	644
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1550	1			T88	21		T207	8		T58	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	35789	1			T88	256		T58	258		T187	6
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1474	1			T51	3		T48	2		T37	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	54490	1			T51	166		T107	1		T188	940
auto[1]	auto[0]	auto[0:524287]	auto[0]	489	1			T21	2		T55	6		T35	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	4451	1			T21	71		T55	54		T35	19
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	386	1			T35	2		T88	12		T89	4
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1877	1			T35	47		T89	11		T107	37
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	384	1			T16	2		T51	4		T48	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2737	1			T51	149		T48	73		T88	437
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	339	1			T16	5		T35	2		T51	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	4040	1			T35	24		T51	22		T48	26
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	364	1			T35	1		T88	10		T89	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2892	1			T35	70		T89	9		T107	55
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	449	1			T35	1		T51	2		T88	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2335	1			T35	18		T51	82		T65	34
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	429	1			T35	3		T48	1		T88	36
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2115	1			T35	34		T48	31		T58	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	446	1			T51	4		T88	6		T89	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2281	1			T51	69		T89	14		T65	14
auto[1]	auto[1]	auto[0:524287]	auto[0]	69	1			T52	3		T37	1		T66	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	508	1			T37	10		T66	4		T68	14
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	76	1			T99	1		T38	1		T205	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	454	1			T99	23		T38	50		T276	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	100	1			T106	3		T205	6		T49	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	331	1			T49	26		T210	13		T182	10
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	68	1			T51	1		T88	5		T65	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	323	1			T51	26		T65	86		T97	40
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	111	1			T52	9		T88	9		T106	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	478	1			T99	4		T205	2		T221	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	108	1			T273	2		T66	1		T220	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	550	1			T273	30		T66	4		T220	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	68	1			T88	3		T58	1		T187	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	327	1			T58	4		T187	1		T66	5
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	99	1			T107	1		T188	1		T66	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	903	1			T107	18		T188	2		T66	17

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2056724	1			T13	1		T15	3		T16	553
auto[0]	auto[0]	auto[1]	1187486	1			T15	1529		T21	1		T22	371
auto[0]	auto[1]	auto[0]	431564	1			T64	5		T52	161		T35	258
auto[0]	auto[1]	auto[1]	6739	1			T207	10		T65	2		T273	1
auto[1]	auto[0]	auto[0]	25486	1			T16	6		T21	72		T55	57
auto[1]	auto[0]	auto[1]	528	1			T16	1		T21	1		T55	3
auto[1]	auto[1]	auto[0]	4468	1			T52	11		T51	27		T88	15
auto[1]	auto[1]	auto[1]	105	1			T52	1		T88	2		T106	1